Ceramic Materials Or Glass (epo) Patents (Class 257/E23.113)
  • Patent number: 11964919
    Abstract: A method for manufacturing active metal-brazed a nitride ceramics substrate having excellent joining strength, includes: a step of preparing a mixed raw material; a step of forming a green sheet of the mixed raw material by a tape casting method; a step of removing a binder by performing degreasing; a step of performing sintering; a step of forming an aluminum nitride sintered substrate by performing gradual cooling; and a step of printing a conductive wiring pattern with active metal paste on the aluminum nitride sintered substrate.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 23, 2024
    Assignee: ZONE INFINITYCO., LTD.
    Inventor: Inchul Cho
  • Patent number: 11746058
    Abstract: A cubic boron nitride (cBN)-based composite including about 30-65 vol. % cBN, about 15-45 vol. % titanium (Ti)-containing binders, about 2-20 vol. % zirconium dioxide (ZrO2), about 3-15 vol. % cobalt-tungsten-borides (CoxWyBz), and about 2-15 vol. % aluminum oxide (Al2O3).
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: September 5, 2023
    Assignee: DIAMOND INNOVATIONS, INC.
    Inventors: Rui Shao, Lawrence Dues
  • Patent number: 11746057
    Abstract: A cubic boron nitride (cBN)-based composite including about 30-65 vol. % cBN, about 3-30 vol. % zirconium (Zr)-containing compounds, about 0-10 vol. % cobalt-tungsten-borides (CoxWyBz), about 2-30 vol. % aluminum oxide (Al2O3), about 0.5-10 vol. % tungsten borides, and less than or equal to about 5 vol. % aluminum nitride (AlN).
    Type: Grant
    Filed: January 23, 2021
    Date of Patent: September 5, 2023
    Assignee: DIAMOND INNOVATIONS, INC.
    Inventors: Rui Shao, Lawrence Dues
  • Patent number: 11493743
    Abstract: An optical unit for a laser processing system includes a laser diode including a plurality of laser emitters which emit laser light, a lens unit including a plurality of lenses, a holding block having a light-transmitting property, and a light-shielding film. The holding block and the laser diode are bonded to each other with a first adhesive, and the lens unit and the holding block are bonded to each other with a second adhesive. The light-shielding film is located between the lens unit and the holding block.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 8, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takayuki Kai, Kouki Ichihashi
  • Patent number: 11420905
    Abstract: The present invention focuses on a silicon nitride substrate having high mechanical strength, high thermal conductivity and the like, and takes advantage of such properties to provide: a ceramic substrate capable of providing improvement in a bonding property between a silicon nitride substrate and a ceramic layer which uses a dielectric ceramic material capable of being simultaneously sintered with a low-resistance conductive material such as a low-melting metal (Ag or Cu); and a method for producing the ceramic substrate. The ceramic substrate of the present invention is obtained by stacking and bonding a silicon nitride substrate and a ceramic layer composed of a dielectric ceramic material, wherein: the dielectric ceramic material contains Mg, Al, and Si as main ingredients, and Bi or B as an accessory ingredient; and the ceramic layer includes a region with a high Si element concentration at a bonding interface with the silicon nitride substrate.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: August 23, 2022
    Assignee: HITACHI METALS, LTD.
    Inventors: Hiroyuki Itoh, Shinroh Itoh
  • Patent number: 10280284
    Abstract: A powder essentially composed of aggregates based on boron nitride, the powder exhibiting an overall chemical composition, as percentages by weight, including between 40 and 45% of boron, between 53 and 57% of nitrogen, less than 400 ppm by weight of calcium, less than 5 %, in total, of other elements and more than 90% of boron nitride, limit included, as percentage by weight and on the basis of the combined crystalline phases, a mean circularity of greater than or equal to 0.90, a median pore size of less than or equal to 1.5 ?m and an apparent porosity of less than or equal to 55%.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 7, 2019
    Assignee: SAINT-GOBAIN CENTRE DE RECHERCHES ET D'ETUDES EUROPEEN
    Inventors: Nabil Nahas, Elodie Bahon, Yves Boussant-Roux
  • Patent number: 10267989
    Abstract: A substrate locally pre-structured for the production of photonic components including a solid part made of silicon; a first localised region of the substrate, including a heat dissipation layer, produced in a localised manner on the surface of the solid part and made of a material of which the refractive index is less than that of silicon; a wave guide on the heat dissipation layer; a second localised region of the substrate, including an oxide layer produced in a localised manner on the surface of the solid part, the oxide having a heat conductivity less than that of the material of the heat dissipation layer; a wave guide on the oxide layer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 23, 2019
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Karim Hassan, Corrado Sciancalepore, Helene Duprez, Badhise Ben Bakir
  • Patent number: 8779584
    Abstract: A semiconductor apparatus equipped with at least one semiconductor element includes a metallic plate bonded to an upper surface of the semiconductor element and a conductor plate, bonded to the metallic plate and serving as an electric current path of the semiconductor apparatus. The conductor plate and the metallic plate are bonded to each other by laser welding at a part other than a part directly above the semiconductor element. As a result, heat damage caused by laser welding can be reduced.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: July 15, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Toshiyuki Yokomae, Katsumichi Ueyanagi, Eiji Mochizuki, Yoshinari Ikeda
  • Patent number: 8704361
    Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Asahi Glass Company, Limited
    Inventor: Hiroki Takahashi
  • Patent number: 8283773
    Abstract: A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Shogo Mori, Eiji Kono, Keiji Toh
  • Patent number: 8049316
    Abstract: A semiconductor package is provided with a package body including a base part and a semiconductor device housing part housing a semiconductor device. An electric terminal electrically connected to the device is provided in the housing part and is exposed to an outer surface. A high heat transfer element is arranged from a heat generating part corresponding position corresponding to a heat generating part of the device to a position outside the corresponding position in the base part. The base part is configured by contacting a plurality of thin sheets mutually closely with each other and by bonding integrally with each other. The high heat transfer element includes particles configured by a material having a thermal conductivity higher than that of the base part and dispersed in the base part. The particles are dispersed between two mutually adjacent thin sheets among the thin sheets.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: November 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Patent number: 7855449
    Abstract: A cooling device for cooling a light-emitting semiconductor device, such as a LED device (20), comprises a ceramic plate (15) having coolant-conveying channels (12) incorporated therein. The ceramic plate (15) is adapted for forming an integral part of the optical system of the light-emitting semiconductor device (20) and to cool a light-emitting portion (26) of the light-emitting semiconductor device (20). A method of forming a cooling device comprises the steps of forming a charge of ceramic particles, embossing the charge with a stamp to form coolant-conveying channels in the charge, hardening the charge, and providing a cover on top of the channels to seal them.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: December 21, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jan De Graff, Celine Catherine Sarah Nicole, Marcus Antonius Verschuuren, Hans Van Sprang, Theo Arnold Kop, Johan Marra, Ronald Martin Wolf
  • Patent number: 7808073
    Abstract: A network electronic component comprises a network-electronic-component substrate, a thin-film passive element provided on the substrate, and a plurality of external connection electrodes provided on the substrate in connection with the thin-film passive element.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: October 5, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Shinji Wakisaka
  • Patent number: 7598535
    Abstract: An LED assembly includes a packaged LED module (30) and a heat dissipation device (50). The LED module includes at least an LED die therein and a plurality of conductive pins (32, 34) extending downwardly from a bottom portion thereof. The heat dissipation device is thermally and electrically connected with the at least an LED die. The heat dissipation device defines at least a mounting hole (542) therein. At least one of the conductive pins is fittingly received in the at least a mounting hole and thermally and electrically connects with the heat dissipation device.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: October 6, 2009
    Assignee: Foxconn Technology Co., Ltd.
    Inventors: Tseng-Hsiang Hu, Yeu-Lih Lin, Li-Kuang Tan
  • Patent number: 7582511
    Abstract: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: September 1, 2009
    Assignee: Touch Micro-System Technology Inc.
    Inventor: Chen Hsiung Yang
  • Patent number: 7521779
    Abstract: A multi-layer structure including a base insulating layer and a thin metal film layer (seed layer) is prepared. A plating resist layer is formed to have a prescribed pattern on the upper surface of the thin metal film layer. A metal plating layer is formed on the thin metal film layer exposed by electroplating. Then, the plating resist layer is removed, and the thin metal film layer in the region having the plating resist layer is removed. In this way, a conductive pattern including the thin metal film layer and the metal plating layer is formed. The upper surface of the base insulating layer in the region without the conductive pattern is subjected to roughening treatment. A cover insulating layer is formed on the upper surfaces of the base insulating layer and the conductive pattern. In this way, a printed circuit board is completed.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: April 21, 2009
    Assignee: Nitto Denko Corporation
    Inventors: Tadao Ookawa, Mitsuru Honjo, Takashi Oda
  • Publication number: 20090091020
    Abstract: A co-fired ceramic module includes a ceramic substrate and at least one heat-emitting device. The ceramic substrate has at least one high thermal conductivity material. The heat-emitting device is disposed on the ceramic substrate. The substrate further includes a cavity and the heat-emitting device is disposed in the cavity.
    Type: Application
    Filed: April 21, 2008
    Publication date: April 9, 2009
    Inventors: Chih-Hung WEI, Yu-Ping HSIEH
  • Patent number: 7514782
    Abstract: An objective is to provide a reliability-improved semiconductor device in which heat radiation characteristics are superior, and warpage of the semiconductor device occurring due to heat generation of a semiconductor chip or to varying of the usage environment is also suppressed. The semiconductor device is provided that includes a thermal-conductive sheet 3 formed on a base board 4, including thermal-conductive resin 6, a heat sink 2 provided on the base board 4 through the thermal-conductive sheet 3, a semiconductor chip 1 mounted on the heat sink 2, and a ceramic-embedded region 31 selectively provided in a region of the thermal-conductive sheet 3 under the semiconductor chip 1, including a ceramic component 5. In this semiconductor device, superior thermal conductivity can be ensured, and warpage and peeling in the semiconductor device occurring due to heat generation of the semiconductor chip or to varying of the usage environment can also be reduced.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: April 7, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiki Hiramatsu, Kei Yamamoto, Atsuko Fujino, Hiromi Ito
  • Publication number: 20090001546
    Abstract: An electrically isolated and thermally conductive double-sided pre-packaged integrated circuit component exhibiting excellent heat dissipative properties, durability and strength, and which can be manufactured at a low cost includes electrically insulated and thermally conductive substrate members having outer surfaces, ultra-thick thick film materials secured to the outer surfaces of the substrate members and a lead member and a transistor member positioned between the substrate members.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Lynda G. Flederbach, Rick A. Weed, Bradley H. Carter, Erich W. Gerbsch, John K. Isenberg, Carl W. Berlin
  • Publication number: 20070161155
    Abstract: The present invention provides a Wafer Level Chip Scale Packaging structure including a die, at least one passive component, a combining layer, an isolating layer, at least one connecting wire, an internal pad and a passivation layer. The die includes a shallow connecting pad, an internal pad and an electrical component. The passive component is formed on one side of the die. The combining layer increases the binding force between the passive component and the die. The part surface on the other side of the die is overlaid with the isolation layer. The part surface of the isolation layer and the internal pad is overlaid with the connecting wire to electrically connect to the internal pad, and the passivation layer is used for protecting the die.
    Type: Application
    Filed: May 17, 2006
    Publication date: July 12, 2007
    Inventor: Chen-Hsiung Yang
  • Patent number: 7239016
    Abstract: A semiconductor device includes a heat generation element; a bonding member; first and second heat radiation plates disposed on first and second sides of the heat generation element through the bonding member; a heat radiation block disposed between the first heat radiation plate and the heat generation element through the bonding member; and a resin mold. The heat radiation block has a thickness in a range between 0.5 mm and 1.5 mm. The semiconductor device has high reliability of the bonding member.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: July 3, 2007
    Assignee: Denso Corporation
    Inventors: Naohiko Hirano, Nobuyuki Kato, Kuniaki Mamitsu, Yoshimi Nakase