Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.

Abstract: An apparatus includes a radio-frequency die with shielding through-silicon vias and a die backside lattice lid that shield a sector in the RF die from radio - and electromagnetic interference.

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract: Devices and circuits related to Electrostatic discharge (ESD) and Electromagnetic compatibility (EMC) are herein described. An ESD protection device is incorporated into a transistor in order to protect the gate of the transistor from excessive current loads related to ESD or EMC events. In an implementation, a device includes a first diode and a second diode that are electrically connected via their respective cathodes. The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode in order to divert excessive current through the second diode.

Abstract: A semiconductor device has a base carrier having first and second opposing surfaces. The first surface of the base carrier is etched to form a plurality of cavities and multiple rows of base leads between the cavities extending between the first and second surfaces. A second conductive layer is formed over the second surface of the base carrier. A semiconductor die is mounted within a cavity of the base carrier. A first insulating layer is formed over the die and first surface of the base carrier and into the cavities. A first conductive layer is formed over the first insulating layer and first surface of the base carrier. A second insulating layer is formed over the first insulating layer and first conductive layer. A portion of the second surface of the base carrier is removed to expose the first insulating layer and electrically isolate the base leads.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die.

Abstract: A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal.

Abstract: A semiconductor device and method of manufacturing has a substrate having a plurality of metal layers. At least one metal layer is exposed on at least one side surface of the semiconductor device. A die is coupled to the substrate. A mold compound encapsulates the die and a top surface of the substrate. A conductive coating is applied to the mold compound and to at least one metal layer exposed on at least one side surface of the substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a dielectric layer on the conductive columns, applying a conductive shield layer on the dielectric layer, and exposing the conductive columns through the dielectric layer and the conductive shield layer; forming a base package substrate; mounting a base integrated circuit die on the base package substrate; mounting the tie bar plate, over the base integrated circuit die, conductively coupled to the base package substrate to form the conductive shield layer into an electro-magnetic interference shield; and removing the tie bar plate to expose the conductive columns from the dielectric layer.

Abstract: A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.

Abstract: An electromagnetic interference (EMI) shielding structure for integrated circuit (IC) substrate includes a plurality of conductive contacts, a covering layer, and a sputtered layer. The conductive contacts are formed at the perimeter of a chip area on the IC substrate. The covering layer is formed on the conductive contacts and covers the chip area. A groove is formed on the covering layer for exposing the conductive contacts. The sputtered layer is formed on the covering layer and connected to the conductive contacts. The EMI shielding structure can restrain the interference in the chip area.

Abstract: An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic sheilding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process.

Abstract: A semiconductor package and method of manufacture are provided. The semiconductor package may include a package substrate, a semiconductor chip, a molding member and a grounding member. The package substrate may include a ground pad and a signal pad. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the signal pad of the package substrate. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The grounding member may be arranged on a surface of the molding member. The grounding member may be electrically connected with the ground pad.

Abstract: A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post.

Abstract: A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer.

Abstract: A package structure with ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a carrier having first and second ground structures electrically insulated from one another; a semiconductor component disposed on one surface of the carrier and electrically connected to the first ground structure; and a lid member disposed to cover the carrier and the semiconductor component and electrically connected to the second ground structure. The semiconductor component and the lid member are electrically connected with the first ground structure and the second ground structure, respectively, such that electrostatic charges and electromagnetic waves can be conducted away individually without damaging the semiconductor component, thereby improving yield and reducing the risk of short circuits.

Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

Abstract: A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.

Abstract: In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages.

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract: A method of assembling a magnetoresistive random access memory (MRAM) device includes providing a substrate having an opening. A tape is applied to a surface of the substrate and a first magnetic shield is placed onto the tape and within the substrate opening. An adhesive is applied between the first magnetic shield and the substrate to attach the first magnetic shield to the substrate. An MRAM die is attached to the first magnetic shield and bond pads of the MRAM die are connected to pads on the substrate with wires. A second magnetic shield is attached to a top surface of the MRAM die. An encapsulating material is dispensed onto the substrate, the MRAM die, the second magnetic shield and part of the first magnetic shield, cured, and then the tape is removed. Solder balls then may be attached to the substrate.

Abstract: A module IC package structure includes a substrate unit, a radio frequency unit, an inner shielding unit, an insulative package unit, and an outer shielding unit. The substrate unit includes a circuit substrate. The radio frequency unit includes at least one radio frequency element disposed on and electrically connected to the circuit substrate. The inner shielding unit includes an inner metal shielding layer formed on a predetermined surface of the radio frequency element. The insulative package unit includes an insulative package resin body disposed on the circuit substrate to cover the radio frequency element. The outer shielding unit is formed on the outer surface of the insulative package resin body and electrically connected to the circuit substrate. The inner metal shielding layer is a radio frequency property maintaining layer disposed between the radio frequency element and one part of the outer shielding unit for shielding the radio frequency element.

Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.

Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.

Abstract: An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.

Abstract: A cap for a MEMS package includes a main body having a bottom surface, a top surface, a plurality of accommodations recessed from the bottom surface towards the top surface, and a plurality of slots recessed from the top surface towards the bottom surface in a way that the top surface is defined into a plurality of regions corresponding to the accommodations respectively. After completion of the MEMS package, the package can be cut along the slots into a plurality of MEMS package units, such that the cutting work can be done quickly and the cutting burrs can be minimized.

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract: According to one embodiment, a semiconductor device includes a circuit substrate, a semiconductor element, a sealing resin layer, and a conductive shielding layer. The circuit substrate includes an insulating layer, a plurality of interconnections forming first interconnection layers provided on an upper surface side of the insulating layer, a plurality of interconnections forming second interconnection layers provided on a lower surface side of the insulating layer, and a plurality of vias penetrating from the upper surface to the lower surface of the insulating layer. The semiconductor element is mounted on the upper surface side of the circuit substrate. The conductive shielding layer covers the sealing resin layer and part of an end portion of the circuit substrate. Any of the plurality of vias and the conductive shielding layer are electrically connected.

Abstract: A Power Management Integrated Circuit (PMIC) that includes a substrate, a high-side (HS) region on the substrate, a low-side (LS) region spaced from the first region, a device isolation layer interposed between the HS region and the LS region, a metal interconnection connected to the HS region across the device isolation layer and configured to permit a high-voltage current to flow in the HS region, and at least one electric field shield between the metal interconnection and the device isolation layer. Since the electric field shield is disposed under the metal interconnection, a sufficient breakdown voltage can be ensured for the HS region and the LS region.

Abstract: Provided is a semiconductor module (A), including: a substrate (1) having an electronic component (2) mounted on an upper surface thereof; an encapsulation resin layer (3) having an insulating property, for encapsulating the upper surface; an exterior shielding member (4) having conductivity, for covering a side of the encapsulation resin layer (3) opposite to the substrate (1); and a connection portion (5), which is provided inside the encapsulation resin layer (3), for electrically connecting the exterior shielding member (4) and a ground terminal (13) provided to the substrate (1).

Abstract: An interconnection structure is disposed between a first conductive layer and a second conductive layer substantially parallel to each other. The conductive layer includes a signal trace. The interconnection structure includes a conductor pillar and a shielding wall pillar. The conductor pillar goes through between the two conductive layers and is electrically connected to the signal trace of the first conductive layer. The shielding wall pillar is also disposed between the two conductive layers and located at a portion of an external region surrounding the conductor pillar and electrically coupled to the conductor pillar. The conductor pillar and the shielding wall pillar are disposed in pair or in group. The shielding wall pillar with a shape different from that of the conductor pillar would make the conductor pillar serve as a connection with a designed impedance and the capability of controlling impedance based on the special shape design thereof.

Abstract: Integrated Circuits and methods for reducing thermal neutron soft error rate (SER) of a digital circuit are provided by doping a protection layer on top of the metal layer and in physical contact with the metal layer of the digital circuit, wherein the protection layer is doped with additional thermal neutron absorbing material. The thermal neutron absorbing material can be selected from the group consisting of Gd, Sm, Cd, B, and combinations thereof. The protection layer may comprise a plurality of sub-layers among which a plurality of them containing additional thermal neutron absorbing material.

Abstract: A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising a semiconductor wafer having a multitude of microchips. The multitude of microchips forming a plurality of independently functioning computers, each computer having independent communication capabilities.

Abstract: A semiconductor device is made by mounting a semiconductor wafer to a temporary carrier. A plurality of TSV is formed through the wafer. A cavity is formed partially through the wafer. A first semiconductor die is mounted to a second semiconductor die. The first and second die are mounted to the wafer such that the first die is disposed over the wafer and electrically connected to the TSV and the second die is disposed within the cavity. An encapsulant is deposited over the wafer and first and second die. A portion of the encapsulant is removed to expose a first surface of the first die. A portion of the wafer is removed to expose the TSV and a surface of the second die. The remaining portion of the wafer operates as a TSV interposer for the first and second die. An interconnect structure is formed over the TSV interposer.

Abstract: An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region.

Abstract: A chip package including a shielding layer conformally covering the underlying molding compound for is provided. The shielding layer can smoothly cover the molding compound and over the rounded or blunted, top edges of the molding compound, which provides better electromagnetic interferences shielding and better shielding performance.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.

Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.

Abstract: A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

Abstract: A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.

Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.

Abstract: Provided is a semiconductor device including a wiring board having a first surface on which a board-side ground terminal and a board-side power supply terminal are provided; a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip; a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface; a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal; a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other.

Abstract: A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.