Abstract: An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a component side; mounting a device over the component side; forming a shield connector on the component side adjacent the device; forming a package interconnect on the component side outside a region having the shield connector and the device; applying an encapsulant around the package interconnect, the shield connector, and the device; and mounting a shield structure on the encapsulant, the shield connector, and the device, with the package interconnect partially exposed.

Abstract: A sensor package, and in one embodiment a sensor package for surface mount applications, that comprises a leadframe with an upper and lower surface for receiving a device thereon. Embodiments of the sensor package comprise a first device secured to the upper surface, and a second device secured to the lower surface so as to place connective pads from each of the first device and the second device proximate to one side of the leadframe. The sensor package further comprises a lead that is positioned in the sensor package in a manner that prevents electrical connection with circuitry that is external of the housing. The lead has an end proximate the side of the lead frame where the connective pads are positioned on the upper and lower surfaces. The end configured to receive connections, e.g., wirebonds, from the connective pads in a manner connecting the first device and the second device independent of any external connections of the sensor package.

Abstract: A method for fabricating MEMS package structure includes the following steps. Firstly, a substrate is provided. Next, a plurality of lower metallic layers and first oxide layers are formed to compose a MEMS structure and an interconnecting structure. Next, an upper metallic layer is formed on the MEMS structure and the interconnecting structure. The upper metallic layer has a first opening and a second opening. Next, the first opening and the second opening are employed as etching channels to remove a portion of the first oxide layers so as to form a first cavity surrounding the MEMS structure and form a second cavity above the interconnecting structure. The first cavity communicates with the second cavity. Next, the second opening is sealed in a vacuum environment. Next, a packaging element is formed on the upper metallic layer in a non-vacuum environment to seal the first opening.

Abstract: A micromechanical component having at least two caverns is provided, the caverns being delimited by the micromechanical component and a cap, and the caverns having different internal atmospheric pressures. The micromechanical component and cap are hermetically joined to one another at a first specifiable atmospheric pressure, then an access to at least one cavern is produced, and subsequently the access is hermetically closed off at a second specifiable atmospheric pressure.

Abstract: A method for electrically coupling a first wafer with a second wafer is provided. The method includes bonding the first wafer with the second wafer using a bonding material. The method further includes forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer. The method further includes forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.

Abstract: A semiconductor device comprises a buffer layer 16 of an i-InAlAs layer formed over an SI-InP substrate 14, insulating films 24, 36 of BCB formed over the buffer layer 16, and a coplanar interconnection including a signal line 52 and ground lines 54 formed over the insulating film 36, a cavity 46 is formed in the SI-InP substrate 14, the buffer layer 16 and the insulating film below the signal line 52, and pillar-shaped supports in the cavity 46 support the insulating films 34, 36 which are the ceiling of the cavity 46.

Abstract: A stacked-type chip package structure including a first package structure, a second package structure, and a first molding compound is provided. The first package structure includes a first substrate, and a first chip stacked thereon and electrically connected thereto. The second package structure is stacked on the first package structure, and includes a second substrate, a second chip, and a plurality of solder blocks. The second chip is electrically connected to the second substrate, and the second substrate is electrically connected to the first substrate. The second chip is fixed on the first chip through an adhesive layer. The solder blocks are disposed on the back of the second substrate. The first molding compound is disposed on the first substrate and encapsulates the first package structure and the second package structure. The first molding compound has a recess for exposing the solder blocks.

Abstract: A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first board-on-chip-structure having a first integrated circuit die mounted over a substrate and the substrate having a substrate cavity; mounting a second board-on-chip-structure over the first board-on-chip-structure, the second board-on-chip-structure having a second integrated circuit die mounted under an interposer and the interposer having an interposer cavity; connecting the first board-on-chip-structure to the second board-on-chip-structure with an internal interconnect; and encapsulating the first board-on-chip-structure, the second board-on-chip-structure, and the internal interconnect with an encapsulation.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.

Abstract: A semiconductor device mountable to a substrate includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. A housing at least in part encloses the semiconductor die and the interlayer material. The housing has a recess disposed through the second attachment surface of the electrically conductive attachment region. A dielectric, thermally conductive interlayer material is located in the recess and secured to the housing. A metallic plate is located in the recess and secured to the interlayer material.

Abstract: A micromechanical device having a substrate wafer has at least one first cavity and one second cavity, the cavities being hermetically separated from each other, the first cavity having a different internal atmospheric pressure than the second cavity. The cavities are capped by a thin film cap. A method is for manufacturing a micromechanical device which has a thin film cap having cavities of different internal atmospheric pressures.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode.

Abstract: Use of Pb-free solder has become essential due to the environmental problem. A power module is formed by soldering substrates with large areas. It is known that in Sn-3Ag-0.5Cu which hardly creeps and deforms with respect to large deformation followed by warpage of the substrate, life is significantly shortened with respect to the temperature cycle test, and the conventional module structure is in the situation having difficulty in securing high reliability. Thus, the present invention has an object to select compositions from which increase in life can be expected at a low strain rate. In Sn solder, by doping In by 3 to 7% and Ag by 2 to 4.5%, the effect of delaying crack development at a low strain rate is found out, and as a representative composition stable at a high temperature, Sn-3Ag-0.5Cu-5In is selected. Further, for enhancement of reliability, a method for partially coating a solder end portion with a resin is shown.

Abstract: A process for packaging a plurality of micro-components made on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a cover plate; depositing a metal layer on a face of the cover plate or on a face of the wafer; covering the wafer with the cover plate; applying a contact pressure equal to at least one bar onto the cover plate and onto the wafer; and heating the metal layer during pressing until a seal is obtained, each cavity thus being provided with a sealing area and being closed by a part of the cover plate and/or its metal layer.

Abstract: An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.

Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.

Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.

Abstract: A semiconductor light receiving device includes a light receiving section made of a semiconductor provided on a substrate, an electrode provided on the substrate and configured to apply an electric field to the light receiving section, a resin layer provided above the substrate, the resin layer having an inverted conical opening, the inverted conical opening being located above the light receiving section and having an opening diameter which is smaller than the light receiving section in the vicinity of the light receiving section, is continuously enlarged with the distance from the substrate, and is larger than the light receiving section at a surface of the resin layer, and a light reflecting film made of metal and provided on a bevel of the inverted conical opening, the light reflecting film being electrically isolated from the electrode by a gap formed between the light reflecting film and the electrode. At least a portion of the resin layer located in the gap has a light blocking property.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an inner stacking module die; encapsulating the inner stacking module die with an inner stacking module encapsulation to form an inner stacking module, the inner stacking module encapsulation having an inner stacking module protrusion having a planar protrusion surface; and encapsulating at least part of the inner stacking module encapsulation with an encapsulation having a flat top coplanar with the planar protrusion surface or fully encapsulating the inner stacking module encapsulation.

Abstract: A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer.

Abstract: An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.

Abstract: A semiconductor packaged device, and method of packaging that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract: The microsystems are integrated in a first cavity bounded by at least a substrate and by a top wall formed by at least a part of a first cover. The component has a second cavity bounded by at least the whole of the top wall of the first cavity and by a second cover formed by a thin layer. The second cover can be covered by a coating made of plastic material molded from a casting. The fabrication process of the component comprises deposition, on the whole of the top wall of the first cavity, of a layer of polymer material and annealing of the layer of polymer material. The layer of polymer material acts as sacrificial layer for deposition of the thin layer designed to form the second cover.

Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.

Abstract: A semiconductor package includes at least: a workpiece at least one surface of which is equipped with a device; a wall portion provided along an outer circumference of the device and is spaced apart from the device; and a cover member that is arranged above the device so as to form a first space and is supported by the workpiece via the wall portion, in which the first space includes at least one second space that communicates with an external space.

Abstract: Apparatuses, methods, and systems for improved integrated circuit packages are described. An integrated circuit (IC) package includes a substrate having opposing first and second surfaces, an IC die, a plurality of conductive elements, and an encapsulating material. The substrate has a plurality of contact pads on the first surface that are electrically coupled to a plurality of electrically conductive features on the second surface. The plurality of conductive elements is formed on the first surface of the substrate. The IC die is located on the first surface of the substrate. The encapsulating material encapsulates the IC die and a portion of each element of the plurality of conductive elements.

Abstract: A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module housing 40 has opposite sides with a first side facing the cooling element 4, and a second side 42 having one or more openings and a surface turned away from the power semiconductor module 3. Each of the one or more openings has a border, which is sealed by an internal contact 16, 17, 18, 27, 28, which is electrically connected to the one or more components 5, 6, 7. The internal contact protrudes the module housing 40, such that the internal contact not extends beyond said surface of the second side 42 of the module housing 40.

Abstract: An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect.

Abstract: A hermetic container includes a first substrate, a second substrate opposed to the first substrate, a frame arranged between the first substrate and the second substrate, and a composite member arranged between the first substrate and the second substrate. The frame is composed of a frame member, a first seal bonding material effecting seal bonding between the frame member and the first substrate, and a second seal bonding material effecting seal bonding between the frame member and the second substrate. The composite member is composed of a first member, a first adhesive material bonding the first member and the first substrate to each other, and a second adhesive material bonding the first member and the second substrate to each other.

Abstract: An integrated circuit package is disclosed. The integrated circuit package comprises an integrated circuit die having a plurality of solder bumps; and a substrate comprising a first plurality of contact pads on a first surface and a second plurality of contact pads on a second surface. The plurality of solder bumps on the integrated circuit die is coupled to the first plurality of contact pads on the first surface of the substrate, wherein at least one edge of the substrate is formed after the integrated circuit die is attached to the substrate. According to one embodiment of the invention, the at least one edge of the substrate is formed after excess substrate material is detached at designated areas. According to another aspect of the invention, an assembly fixture is disclosed. An apparatus and method for assembling an integrated circuit package are also disclosed.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: A method of sealing a microelectromechanical system (MEMS) device from ambient conditions is described, wherein the MEMS device is formed on a substrate and a substantially hermetic seal is formed as part of the MEMS device manufacturing process. The method comprises forming a metal seal on the substrate proximate a perimeter of the MEMS device using a method such as photolithography. The metal seal is formed on the substrate while the MEMS device retains a sacrificial layer between conductive members of MEMS elements, and the sacrificial layer is removed after formation of the seal and prior to attachment of a backplane.

Abstract: A high frequency device module of an embodiment of a current invention includes: an insulation substrate in which electrodes are provided on the front surface thereof and a grounding substrate is provided on the rear surface thereof; a high frequency device provided on the insulation substrate with a terminal of the device connected to the electrodes; potting material for covering the high frequency device; and a metallic layer provided on the potting material and connected to the grounding substrate.

Abstract: A semiconductor device with a WLP structure that enables the improvement of heat resistance. A dam layer which spreads over a PI film and an Si substrate for a chip is formed between the Si substrate and a sealing resin so as to surround the chip on all sides. A material for the dam layer is selected so that good adhesion will be obtained between the dam layer and the Si substrate, between the dam layer and the PI film, and between the dam layer and the sealing resin. As a result, even if a crack appears at a portion on a side of the semiconductor device where the Si substrate and the sealed resin are joined in a heating environment, the crack does not run inside the dam layer. This prevents the peeling of the sealing resin or peeling inside the chip and the performance of the semiconductor device is maintained.

Abstract: A semiconductor device is provided, which comprises: a die including an active surface; a multiplicity of bond pads formed on the active surface of the die, wherein a first one of the bond pads is larger than a second one of the bond pads; and a multiplicity of solder bumps, each formed over a corresponding bond pad, wherein the multiplicity of solder bumps include a first solder bump formed over the first bond pad and a second solder bump formed over the second bond pad, the first solder bump having a footprint that is substantially larger than the second solder bump and a maximum diameter that is substantially larger than the second solder bump.

Abstract: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided.

Abstract: A semiconductor substrate of a solid state imaging device is connected to a cover glass, and then a backgrind is performed so as to make the thickness smaller. On a first face of the semiconductor substrate is formed plural units which is constructed of image sensors and plural contact terminals. At positions of the contact terminals, plural through-holes are formed on the bottom side of the semiconductor substrate, and the contact terminals appear on a second surface of the semiconductor substrate. On an interconnection circuit pattern of the assembly substrate are formed stud bumps. When the semiconductor substrate is assembled onto the assembly substrate, the stud bumps enter into the through-holes to contact to the contact terminals. Thus the interconnection circuit pattern is electrically connected to the image sensors.

Abstract: An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation.

Abstract: A micromechanical component has a structure such that a material flow is guided from at least one preferred direction for the purpose of uniformly enveloping the micromechanical component.

Abstract: A packaging method including assembling components on a substrate, manufacturing a lid assembly to include a plurality of integrated covers, and mating the lid assembly to the substrate.

Abstract: A high reliability semiconductor device is provided which can prevent electromigration due to the deposition of metal ions originating from wires. The device includes: a flexible wiring board 11 including a base film 1 and multiple wires 9; a semiconductor chip 5 mounted to the flexible wiring board 11; and a sealing resin 6 disposed between the flexible wiring board 11 and the semiconductor chip 5 so as to at least partially in contact with the wires 9. The sealing resin 6 contains a metal ion binder mixed thereto.

Abstract: A chip package structure includes a substrate, a chip, a first B-stage adhesive, bonding wires, a heat sink and a molding compound. The substrate comprises a first surface, a second surface and a through hole. The chip is arranged on the first surface of the substrate and electrically connected thereto while the through hole of the substrate exposes a portion of the chip. The first B-stage adhesive is arranged between the chip and the first surface of the substrate, and the chip is attached to the substrate through the first B-stage adhesive. The bonding wires are connected between the chip exposed by the through hole and second surface of the substrate. The heat sink is arranged on the first surface of the substrate, covering the chip. The molding compound is arranged on the second surface of the substrate, covering a portion of the substrate and bonding wires.

Abstract: An exemplary semiconductor package includes a substrate, at least one passive component, an insulative layer and a chip. The substrate defines a cavity therein. The at least one passive component is disposed within the cavity, and is electrically connected to the substrate. The insulative layer is received in the cavity, and encases the at least one passive component. The chip is disposed on the insulative layer, and is electrically connected to the substrate. The semiconductor package packaging the at least one passive component within the cavity and under the chip can improve a space usage thereof, thus a packaging scale of the semiconductor package could be reduced.

Abstract: An electronic component package includes a dielectric substrate having a first surface where an electronic component is sealed. A first signal line connecting to the electronic component and a first ground conductor are formed on the first surface of the dielectric substrate. A second signal line connected to an outside connection electrode and a second ground conductor are formed on a second surface of the dielectric substrate. The first ground conductor and the second ground conductor are connected by a plurality of ground conductor via-holes. A substrate-buried signal line connected to the first signal line and the second signal line is provided inside of the dielectric substrate so as to be put between the first ground conductor and the second ground conductor above and below and between the ground conductor via-holes on the right and left.

Abstract: The present invention relates to semiconductor package and the method of making the same. The method of the invention comprises the following steps: (a) providing a first substrate; (b) mounting a first chip onto a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities accommodating top ends of each of the conductive elements; and (e) forming a first molding compound for encapsulating the surface of the first substrate, the first chip and parts of the conductive elements, wherein the height of the first molding compound is smaller than the height of each of the conductive elements. Thus, the first molding compound encapsulates the entire surface of the first substrate, so that the mold flush of the first molding compound will not occur, and the rigidity of the first substrate is increased.

Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.