Abstract: Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced.

Abstract: Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A dynamic quantity sensor device includes: first and second dynamic quantity sensors having first and second dynamic quantity detecting units; and first and second substrates, which are bonded to each other to provide first and second spaces. The first and second units are air-tightly accommodated in the first and second spaces, respectively. A SOI layer of the first substrate is divided into multiple semiconductor regions by trenches. First and second parts of the semiconductor regions provide the first and second units, respectively. The second part includes: a second movable semiconductor region having a second movable electrode, which is provided by a sacrifice etching of the embedded oxide film; and a second fixed semiconductor region having a second fixed electrode. The second sensor detects the second dynamic quantity by measuring a capacitance between the second movable and fixed electrodes, which is changeable in accordance with the second dynamic quantity.

Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

Abstract: A semiconductor integrated circuit includes a semiconductor substrate, one or more devices in or on the semiconductor substrate, and a dielectric layer above the one or more devices, wherein the dielectric layer has openings over at least portions of the one or more devices. The semiconductor integrated circuit also includes plastic packaging material (e.g., plastic granules) on a top surface of the dielectric layer and over the openings. In some implementations, the one or more devices include bi-polar transistors, and the openings in the dielectric layer are located over base-emitter junctions of the bi-polar devices.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract: A method of producing a LED package through controlled wetting.

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: The present invention include a semiconductor device and a method therefor, the method includes disposing a sheet-shaped resin at a side opposite to the chip mounting portion mounting semiconductor chips to be mounted on the chip mounting portion, and forming a resin sealing portion between the sheet-shaped resin and the chip mounting portion, to seal the semiconductor chips. According to an aspect of the present invention, it is possible to provide a semiconductor device and a fabrication method therefor, by which it is possible to reduce the size of the package and to prevent the generation of an unfilled portion in a resin sealing portion or a filler-removed portion or to prevent the exposure of wire from the resin sealing portion.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A tandem solar cell and fabricating method thereof are disclosed. The steps of the fabricating method comprises: a top inverted solar cell having a plurality of inverted solar sub-cells is provided; a bottom normal solar cell having a plurality of normal solar sub-cells accompanying with the inverted solar sub-cells is provided; and processing fit process of the top inverted solar cell and the bottom normal solar cell is executed, wherein an interlayer is disposed between the bottom normal solar cell and the top inverted solar cell, and the interlayer includes a plurality of conductive dots. The plurality of inverted solar sub-cells and normal solar sub-cells are placed with an offset distance from each other, and a plurality of solar sub-cells are formed after the pressing fit process, and the plurality of solar sub-cells are series/parallel connection each other by electrically connecting the plurality of conductive dots.

Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.

Abstract: A method of manufacture of an integrated circuit packaging system includes forming a lead frame including providing a tie bar plate, forming conductive columns on the tie bar plate, forming a dielectric layer on the conductive columns, applying a conductive shield layer on the dielectric layer, and exposing the conductive columns through the dielectric layer and the conductive shield layer; forming a base package substrate; mounting a base integrated circuit die on the base package substrate; mounting the tie bar plate, over the base integrated circuit die, conductively coupled to the base package substrate to form the conductive shield layer into an electro-magnetic interference shield; and removing the tie bar plate to expose the conductive columns from the dielectric layer.

Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.

Abstract: The power semiconductor module (1) comprises several semiconductor components (6, 7, 8), located on a substrate (2). The aim of the invention is to prevent a reduction in the pressure of the substrate against a cooling surface and the resulting loss of cooling arising from deformations. Said aim is achieved, whereby the substrate (2) comprises several substrate regions (3, 4, 5), with one or several connection regions (31, 32), located between substrate regions (3, 4, 5), by means of which the substrate regions (3, 4, 5) are connected such as to move relative to each other.

Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: An integrated circuit package-on-package system includes: mounting an integrated circuit package system having a mountable substrate over a package substrate with the mountable substrate having a mold structure; forming a package encapsulation having a recess over the package substrate and the integrated circuit package system. The present invention also includes: forming an anti-mold flash feature with an extension portion of the package encapsulation and constrained by the mold structure at the bottom of the recess, and partially exposing the mountable substrate in the recess with the anti-mold flash feature formed with the mold structure; and mounting an integrated circuit device over the mountable substrate in the recess.

Abstract: A semiconductor device includes a wiring substrate having a mounting surface on which a semiconductor element is mounted. A portion of the mounting surface exposed from the semiconductor element is covered by a solder-resist layer, and an extension portion of the solder-resist layer extends from a dropping-commencing point of a liquid-state under-filling agent on the portion of the mounting surface exposed from the semiconductor element and into an area of the wiring substrate covered by the semiconductor element. A gap between the semiconductor element and the extension portion of the solder-resist layer is formed to be narrower than the gap between the semiconductor element and the mounting surface of the wiring substrate so that liquid drops of the under-filling agent dropped at the dropping-commencing point are sucked into the gap by a capillary phenomenon.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

Abstract: A method for manufacturing a light-emitting case includes forming a PLED (Polymer Light Emitting Diode) device, disposing the PLED device into a mold, and utilizing the mold to sheathe the PLED device with transparent plastic material in an injection-molding manner. Since the mold has a cavity corresponding to a predetermined shape, the formed transparent plastic material has a geometric appearance corresponding to the predetermined shape.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.

Abstract: Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity.

Abstract: A device having at least one semiconductor component, which is covered by a protective material on its outer surface. The invention provides for the outer surface to be provided with a surface structure so as to enlarge the heat transfer area to the protective material. The invention furthermore relates to a manufacturing method.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an encapsulation system having a mold chase with a buffer layer attached thereto; forming a base integrated circuit package including: providing a base substrate, connecting an exposed interconnect to the base substrate, a portion of the exposed interconnect having the buffer layer attached thereon, mounting a base component over the base substrate, forming a base encapsulation over the base substrate and the exposed interconnect using the encapsulation system; and releasing the encapsulation system providing the portion of the exposed interconnect exposed from the base encapsulation, the exposed interconnect having characteristics of the buffer layer removed.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base panel having a first side with a cavity and a second side opposite the first side; connecting an integrated circuit device and the first side; applying a resist mask having an opening on the second side, the opening offset from the cavity; forming a bump contact in the opening; applying an encapsulation in the cavity over the integrated circuit device and the first side; and forming a package lead by removing a portion of the base panel under the cavity, a flared tip of the package lead intersecting a base side of the encapsulation.

Abstract: A method of manufacture of a base package system includes: forming a substrate strip assembly including: providing a substrate strip having ball lands, mounting an integrated circuit on the substrate strip, and molding a finger structure, having a knuckle region, on the integrated circuit; and singulating a substrate from the substrate strip assembly.

Abstract: A method and device for one or more dimensional input control of different functions in electronic devices is provided. Certain versions of the Present Invention provide a one or more dimensional input force interface control device for cell phones, portable gamers, digital cameras, and other applications. Certain alternate versions of the Present Invention exhibit one or more of the qualities of smallness, low-cost, high reliability, and/or high stability. Certain still alternate versions of the Present Invention provide a three, two or one-dimensional input finger force control device that (1.) accommodates a required ratio between X, Y and Z sensitivities, (2.) has low cross-axis sensitivity, (3.) allows process integration with other sensors and CMOS, (4.) is scalable, (5.) allows convenient solutions for applying an external force, and/or (6.) allows economic manufacturability for high volume consumer markets.

Abstract: In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack.

Abstract: A manufacturing method for a packaging structure of SIP (system in package) includes the following steps. First step is providing a substrate having electronic devices thereon. Second step is covering the electronic devices by a mixture of a molding compound and a conductive polymer precursor so as to form a molding structure, wherein the substrate, the electronic devices and the molding structure forms a collective electronic module. Third step is separating the collective electronic module into a plurality of individual electronic modules. Fourth step is performing a doping step by using a doping element for transforming the conductive polymer precursor in the mixture into a conductive layer near the surface of the molding structure. Therefore, the manufacturing method is optimized for forming a shielding structure of the SIP module.

Abstract: A semiconductor chip package includes a base comprising a die attach region and a mold-lock forming region surrounding the die attach region; a die mounted onto the base within the die attach region; a plurality of line-shaped trenches in the mold-lock forming region; a mold body encapsulating the die; and a mold lock inlaid in each of the line-shaped trenches to securely interlock the mold body to the base.

Abstract: A semiconductor package and method of manufacture has a substrate having an aperture. A semiconductor die is positioned in the aperture of the substrate and attached to a heat spreader by a first adhesive and electrically coupled to the substrate by at least one conductive wire. The heat spreader spans the aperture and is peripherally attached to a bottom surface of the substrate by a second adhesive. An encapsulant encapsulates the aperture, the semiconductor die, and the electrically conductive wire.

Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Abstract: A semiconductor package with a support structure and a fabrication method thereof are provided. With a chip being electrically connected to electrical contacts formed on a carrier, a molding process is performed. A plurality of recessed portions formed on the carrier are filled with an encapsulant for encapsulating the chip during the molding process. After the carrier is removed, the part of the encapsulant filling the recessed portions forms outwardly protruded portions on a surface of the encapsulant, such that the semiconductor package can be attached to an external device via the protruded portions.

Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.

Abstract: A force input control device suitable for high-volume applications such as cell phones, portable gaming devices and other handheld electronic devices along with other applications like medical equipment, robotics, security systems and wireless sensor networks is disclosed. The device can be one-axis or two-axis or three-axis sensitive broadening the range of applications. The device comprises a force sensor die formed within semiconductor substrate and containing a force sensor providing electrical output signal in response to applied external force, and electrical connection elements for mounting and/or wire bonding. Signal conditioning and processing integrated circuit can be integrated within some devices. A package enclosing at least a portion of the force sensor die and comprising a force-transferring element cooperated with the sensor die for transferring an external force to the force sensor die.

Abstract: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.

Abstract: A back-side lamination (BSL) is applied after thinning a microelectronic die. The BSL is configured to be a thermal-expansion complementary structure to a metal wiring interconnect layout that is disposed on the active side of the microelectronic die.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A package and a package assembly for a power device having a high operation voltage and impulse voltage are provided. The package assembly for a power device comprises an assembly wherein the power device is encapsulated and electrically connected to a lead protruding outside the package, and an isolation spacer filling a clearance distance between the package and a heat sink attached to the package.