Device Being Completely Enclosed (epo) Patents (Class 257/E23.124)
  • Patent number: 10773088
    Abstract: Systems, devices, and techniques for establishing communication between two medical devices are described. In one example, an implantable medical device comprises communication circuitry, therapy delivery circuitry, and processing circuitry configured to initiate a communication window during which the implantable second medical device is capable of receiving the information related to a cardiac event detected by a first medical device, the communication window being one of a plurality of communication windows defined by a communication schedule that corresponds to a transmission schedule in which the first medical device is configured to transmit the information, control the communication circuitry to receive, from the first medical device, the information related to the cardiac event that is indicative of a timing of the cardiac event with respect to a timing of the communication window, schedule and control delivery of a therapy according to the information related to the cardiac event.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: September 15, 2020
    Assignee: Medtronic, Inc.
    Inventors: James K. Carney, Saul E. Greenhut, Jonathan L. Kuhn, James D. Reinke, David J. Peichel, James W. Busacker
  • Patent number: 10366947
    Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 9748163
    Abstract: A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 29, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Soon Wei Wang, How Kiat Liew, Chee Hiong Chew, Francis J. Carney
  • Patent number: 9640506
    Abstract: An embodiment for manufacturing electronic devices is proposed. The embodiment includes the following phases: a) forming a plurality of chips in a semiconductor material wafer including a main surface; each chip includes respective integrated electronic components and respective contact pads facing the main surface; said contact pads are electrically coupled to the integrated electronic components; b) attaching at least one conductive ribbon to at least one contact pad of each chip; c) covering the main surface of the semiconductor material wafer and the at least one conductive ribbon with a layer of plastic material; d) lapping an exposed surface of the layer of plastic material to remove a portion of the plastic material layer at least to uncover portions of the at least one conductive ribbon, and e) sectioning the semiconductor material wafer to separate the chips.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 2, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 9496171
    Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: November 15, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Matthew David Romig, Steven Alfred Kummerl, Wei-Yan Shih
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9018747
    Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Kyocera Corporation
    Inventor: Michikazu Nagata
  • Patent number: 9013035
    Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8952523
    Abstract: An integrated circuit package apparatus includes a packaging substrate, an integrated circuit coupled to an upper side of the packaging substrate, an array of contacts coupled to an underside of the packaging substrate for electrically coupling the integrated circuit to a circuit board, and a lid coupled to the upper side of the packaging substrate. In one form, the lid includes a central portion lying on a first plane, corner areas lying on a second plane, and arcuate wall portions disposed between and interconnecting the corner areas and the central portion. Other forms of the lid are provided.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: February 10, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Mudasir Ahmad, Mohan R. Nagar, Weidong Xie
  • Patent number: 8940587
    Abstract: Novel die seals control contact of a mold material with the surfaces of a semiconductor die during encapsulation, reducing stresses due to a mismatch of the coefficient of thermal expansion of the encapsulant and the semiconductor die, thereby reducing cracking of the semiconductor die, resulting in increased yields and lower costs.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: January 27, 2015
    Assignee: Amkor Technology, Inc.
    Inventor: Bora Baloglu
  • Patent number: 8878361
    Abstract: A leadless package system includes: an integrated circuit die having contact pads; external contact terminals with a conductive layer and an external coating layer; connections between contact pads in the integrated circuit die and the external contact terminals; and an encapsulant encapsulates the integrated circuit die and the external contact terminals including the external coating layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Heap Hoe Kuan
  • Patent number: 8853865
    Abstract: The size and thickness of a semiconductor device are reduced. A semiconductor package with a flip chip bonding structure includes: a semiconductor chip having a main surface with multiple electrode pads formed therein and a back surface located on the opposite side thereto; four lead terminals each having an upper surface with the semiconductor chip placed thereover and a lower surface located on the opposite side thereto; and a sealing body having a main surface and a back surface located on the opposite side thereto. In this semiconductor package, the distance between adjacent first lower surfaces of the four lead terminals exposed in the back surface of the sealing body is made longer than the distance between adjacent upper surfaces thereof.
    Type: Grant
    Filed: August 15, 2010
    Date of Patent: October 7, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Narita
  • Patent number: 8803303
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Patent number: 8796840
    Abstract: A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: August 5, 2014
    Assignee: Vishay General Semiconductor LLC
    Inventors: Wan-Lan Chiang, Kuang Hann Lin, Chih-Ping Peng
  • Patent number: 8791561
    Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 29, 2014
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
  • Patent number: 8749038
    Abstract: A substrate module having an embedded phase-locked loop is cooperated with at least one function unit mounted thereon for forming an integrated system. The substrate module includes a base, a multi-layer structure, a built-in circuit unit, and an external circuit unit. The built-in circuit unit is integrated inside the multi-layer structure and the multi-layer structure is formed in the base. The external circuit unit is mounted on the upper surface of the base and is electrically coupled to the built-in circuit unit for jointly forming a phase-locked loop, so as to cooperate with the function unit.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: June 10, 2014
    Assignee: Azurewave Technologies, Inc.
    Inventors: Chung-Er Huang, Nan-Cheng Chen
  • Patent number: 8703537
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 22, 2014
    Assignee: NeuroNexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Ning Gulari
  • Patent number: 8686550
    Abstract: A pressure sensor package is provided that reduces the occurrence of micro gaps between molding material and metal contacts that can store high-pressure air. The present invention provides this capability by reducing or eliminating interfaces between package molding material and metal contacts. In one embodiment, a control die is electrically coupled to a lead frame and then encapsulated in molding material, using a technique that forms a cavity over a portion of the control die. The cavity exposes contacts on the free surface of the control die that can be electrically coupled to a pressure sensor device using, for example, wire bonding techniques. In another embodiment, a region of a substrate can be encapsulated in molding material, using a technique that forms a cavity over a sub-portion of the substrate that includes contacts. A pressure sensor device can be electrically coupled to the exposed contacts.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William G. McDonald, Alexander M. Arayata, Philip H. Bowles, Stephen R. Hooper
  • Patent number: 8680692
    Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 25, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 8680688
    Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 25, 2014
    Assignee: SK Hynix Inc.
    Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Byoung Do Lee, Yu Hwan Kim
  • Patent number: 8658465
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: February 25, 2014
    Assignee: NeuroNexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Gulari
  • Patent number: 8637966
    Abstract: In a QFP with a chip-stacked structure in which a lower surface of a die pad is exposed from a lower surface of a sealing member, a semiconductor chip having a BCB film, which is made of a polymeric material containing at least benzocyclobutene in its backbone as an organic monomer and formed on its surface, is mounted at a position (second stage) that is away from the die pad. As a result, even when moisture invades through the interface between the die pad and the sealing member, it is possible to prolong the time required for the moisture to reach the semiconductor chip, and subsequently to make moisture absorption defect less likely to occur.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 28, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Kanemoto
  • Patent number: 8637976
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 28, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20130334682
    Abstract: The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers.
    Type: Application
    Filed: September 13, 2012
    Publication date: December 19, 2013
    Applicant: SK HYNIX INC.
    Inventor: Seung Jee KIM
  • Patent number: 8598696
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: December 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joseph C. Fjelstad, Para K. Segaram, Kevin P. Grundy, Inessa Obenhuber
  • Patent number: 8558364
    Abstract: An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 15, 2013
    Assignee: Innovative Micro Technology
    Inventor: Jeffery F. Summers
  • Patent number: 8558367
    Abstract: A semiconductor module includes: an insulating plate; a plurality of metal patterns formed on the insulating plate and spaced apart from each other; a power device chip solder-joined on one the metal pattern; a lead frame solder-joined on the metal pattern to which the power device chip is not solder-joined, and on the power device chip; an external main electrode provided to an outer casing, and joined by wire bonding to the lead frame above the metal pattern to which the power device chip is not joined; and a sealing resin formed by potting to seal the power device chip, the lead frame, and the metal patterns.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 15, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tatsuo Ota, Toshiaki Shinohara
  • Patent number: 8552543
    Abstract: A semiconductor package that includes a conductive clip having an interior surface that includes a plurality of spaced raised portions, a semiconductor device having a first major surface that includes a plurality of spaced depressions each receiving one of the raised portions in the interior thereof, and a conductive adhesive disposed between each raised portion and a respective interior surface of a depression.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: October 8, 2013
    Assignee: International Rectifier Corporation
    Inventor: Mark Pavier
  • Patent number: 8518752
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package base having an inward base side and an outward base side; mounting a device over the inward base side and connected to the outward base side; connecting a silicon interposer having a through silicon via to the device and having an external side facing away from the device; and applying an encapsulant around the device, over the package base, and over the silicon interposer with the external side substantially exposed, the encapsulant having a protrusion over the outward base side.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: August 27, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, DaeSik Choi
  • Patent number: 8519519
    Abstract: A semiconductor device includes a lead frame that has a die interconnect portion and at least first and second die pads. The die interconnect portion is isolated from the die pads. The device also includes a first die and a second die attached to the first and second die pads and electrically connected to each other by way of the die interconnect portion. The first die is encapsulated in a first medium and the second die is encapsulated in a second medium, the first medium being different from the second medium.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 27, 2013
    Assignee: Freescale Semiconductor Inc.
    Inventors: Beng Siong Lee, Guat Kew Teh, Wai Keong Wong
  • Patent number: 8492887
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jayby Agno, Erwin Aguas Sangalang, Dexter Anonuevo, Ramona Damalerio
  • Patent number: 8486744
    Abstract: The present disclosure provides a method for fabricating a MEMS device including multiple bonding of substrates. In an embodiment, a method includes providing a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, providing a semiconductor substrate including a second bonding layer, and providing a cap including a third bonding layer. The method further includes bonding the MEMS substrate to the semiconductor substrate at the first and second bonding layers, and bonding the cap to the semiconductor substrate at the second and third bonding layers to hermetically seal the MEMS substrate between the cap and the semiconductor substrate. A MEMS device fabricated by the above method is also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Lin, Chia-Hua Chu, Li-Cheng Chu, Yuan-Chih Hsieh, Chun-Wen Cheng
  • Patent number: 8482109
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral contact layer surrounding the peripheral lead with a non-horizontal side exposed from the peripheral contact layer; forming an inner lead and a paddle non-planar with the peripheral lead; mounting an integrated circuit to the paddle; and forming an encapsulation covering the integrated circuit and exposing the inner lead, the paddle, and the non-horizontal side.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 9, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Emmanuel Espiritu
  • Patent number: 8461677
    Abstract: Magnetic field sensors and associated methods of manufacturing the magnetic field sensors include molded structures to encapsulate a magnetic field sensing element and an associated die attach pad of a lead frame and to also encapsulate or form a magnet or a flux concentrator.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 11, 2013
    Assignee: Allegro Microsystems, LLC
    Inventors: Virgil Ararao, Nirmal Sharma, Raymond W. Engel, Jay Gagnon, John Sauber, William P. Taylor, Elsa Kam-Lum
  • Patent number: 8436457
    Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: May 7, 2013
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 8421209
    Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: April 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Patent number: 8410601
    Abstract: An RF package includes a substrate mountable on a base plate, a non-conductive cover overlying the substrate, and quasi-serpentine stepped source leads attached to an upper surface of the substrate and extending from at least one of a pair of opposite sides of the upper surface of the substrate to tapered lower surfaces of the cover. The cover includes a recess to receive the substrate. The recess includes stress distribution surface areas to engage and press outer edge portions of opposite sides of the substrate against a base plate or heat sink. The tapered lower surfaces of the cover engage with and press against the stepped source leads when securing the RF package to the base plate or heat sink using one or more fasteners or bolts. The cover includes structural features to improve preferential deformation when a mounting force is applied.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: April 2, 2013
    Assignee: Microsemi Corporation
    Inventor: Benjamin A. Samples
  • Patent number: 8399977
    Abstract: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electr
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: March 19, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Kunimoto, Akihiko Tateiwa
  • Patent number: 8304268
    Abstract: A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8304891
    Abstract: A semiconductor package device, a semiconductor package structure, and fabrication methods thereof are provided, which mainly includes disposing a plurality of semiconductor chips on a wafer formed with TSVs (Through Silicon Vias) and electrically connecting the semiconductor chips to the TSVs; encapsulating the semiconductor chips with an encapsulant; and disposing a hard component on the encapsulant. The hard component ensures flatness of the wafer during a solder bump process and provides support to the wafer during a singulation process such that the wafer can firmly lie on a singulation carrier, thereby overcoming the drawbacks of the prior art, namely difficulty in mounting of solder bumps, and difficulty in cutting of the wafer.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: November 6, 2012
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Chin-Huang Chang, Chien-Ping Huang, Chih-Ming Huang, Jung-Pin Huang
  • Patent number: 8304923
    Abstract: A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: November 6, 2012
    Assignee: ADL Engineering Inc.
    Inventors: Dyi-Chung Hu, Yu-Shan Hu, Chih-Wei Lin
  • Patent number: 8293588
    Abstract: A method of packaging an electronic device includes providing a patterned dielectric layer with an area sized to receive a first die, and another area sized to receive a second die, placing the first and second dies within the first and second areas, encapsulating the dies with an encapsulating material that has a different composition from the dielectric layer, forming a first signal line between the dies, forming a second signal line to the first die, and forming an additional signal line to the first die. The dielectric layer is disposed between the first signal line and the encapsulating material, the electronic device transmits a signal in an approximate range of 1 GHz to 100 GHz along the second signal line, and a signal that does not exceed approximately 900 MHz along the additional signal line.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 23, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jinbang Tang
  • Patent number: 8288873
    Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Byoung Do Lee, Yu Hwan Kim
  • Patent number: 8288858
    Abstract: This semiconductor device has a frame including a bed portion on which a semiconductor chip is mounted, lead groups arranged in an outer peripheral portion, first bus bars, second bus bars and a rectifying bus bar. The first bus bars and the second bus bars are arranged between the bed portion and the lead groups. The rectifying bus bar is arranged in a region where the second bus bar is not arranged. Wire bonding is not performed on the rectifying bus bar. The rectifying bus bar includes a third bus bar having at least one end joined to a lead or a hanging pin and/or a fourth bus bar formed by extending the first bus bar in an outer peripheral direction in which the leads are arranged. The semiconductor device is provided in which deformation and damage of bonding wires when molding a resin sealed body are prevented.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Taku Tsumori
  • Patent number: 8288211
    Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate. At least one of the substrates may include a raised feature formed under at least one of the metal layers. One of the metal layer may have a diffusion barrier layer and a “keeper” layer formed thereover, wherein the keeper layers keeps the metal confined to a particular area. By using such a “keeper” layer, the substrate components may be heated to clean their surfaces, without activating or spending the bonding mechanism.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Innovative Micro Technology
    Inventors: John S. Foster, Alok Paranjpye, Douglas L. Thompson
  • Patent number: 8273607
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: September 25, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Soo-San Park, Sang-Ho Lee, DaeSik Choi
  • Patent number: 8269332
    Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: September 18, 2012
    Assignee: Sumitomo Bakelite Company, Ltd.
    Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
  • Patent number: 8241950
    Abstract: The method of the preferred embodiments includes the steps of providing a base having a frame portion and a center portion; building a preliminary structure coupled to the base; removing a portion of the preliminary structure to define a series of devices and a plurality of bridges; removing the center portion of the base such that the frame portion defines an open region, wherein the plurality of bridges suspend the series of devices in the open region defined by the frame; and encapsulating the series of devices. The method is preferably designed for the manufacture of semiconductor devices, and more specifically for the manufacture of encapsulated implantable electrodes. The method, however, may be alternatively used in any suitable environment and for any suitable reason.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Neuronexus Technologies, Inc.
    Inventors: David S. Pellinen, Jamille Farraye Hetke, Daryl R. Kipke, Kc Kong, Rio J. Vetter, Mayurachat Gulari
  • Publication number: 20120187552
    Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.
    Type: Application
    Filed: April 3, 2012
    Publication date: July 26, 2012
    Inventors: Chad A. Cobbley, Cary J. Baerlocher