Coating Being Directly Applied To Semiconductor Body, E.g., Passivation Layer (epo) Patents (Class 257/E23.132)
  • High performance CMOS transistors using PMD liner stress
    Patent number: 7192894
    Abstract: A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Rajesh Khamankar, Douglas T. Grider