Abstract: Disclosed is a coating comprising a polymeric layer, wherein the polymeric layer comprises a reaction product of a first monomer comprising two or more aromatic acetylene groups and a second monomer comprising two or more cyclopentadienone groups, or a cured product of the reaction product. The coating may or may not additionally contain a crosslinker and/or a thermal acid generator. Optical thin films made from the coatings exhibit refractive indices that make them useful as interlayers for matching refractive indices between adjacent layers of display devices; thereby improving device output efficiency.

Abstract: The present invention relates to an adhesive composition, which comprises an epoxy resin; and a polyimide comprising a repeating unit. The repeating unit comprises a first repeating unit represented by formula (1) and a second repeating unit represented by formula (2): wherein X1, Y, Z, m, and n are as defined herein, the weight ratio of polyimide to the total amount of the epoxy resin is 50% to 100%, and in the epoxy resin, the proportion of the epoxy resin having a weight average molecular weight of less than 400 Da accounts for 12 to 40% by weight of the total amount of the epoxy resin. The adhesive formed by the adhesive composition of the present invention has a relatively high glass transition temperature.

Abstract: Methods and structures corresponding to superconducting apparatus including superconducting layers and traces are provided. A method for forming a superconducting apparatus includes forming a first dielectric layer on a substrate by depositing a first dielectric material on the substrate and curing the first dielectric material at a first temperature. The method further includes forming a first superconducting layer comprising a first set of patterned superconducting traces on the first dielectric layer. The method further includes forming a second dielectric layer on the first superconducting layer by depositing a second dielectric material on the first superconducting layer and curing the second dielectric material at a second temperature, where the second temperature is lower than the first temperature. The method further includes forming a second superconducting layer comprising a second set of patterned superconducting traces on the second dielectric layer.

Abstract: Thermal chemical vapor deposition processes and coated articles are disclosed. The coated article includes a surface having a surface impurity and a coating on the surface formed by thermally reacting a gas. In comparison to a comparable coating without the surface impurity, the coating on the surface has substantially the same level of adhesion, corrosion resistance over 24 hours in 6M HCl, corrosion resistance over 72 hours in NaClO, and electrochemical impedance spectroscopy results. Additionally or alternatively, the surface impurity has properties that reduce or eliminate adhesion of a comparative coating produced by decomposition of silane on a comparative surface following exposure of the surface to a temperature.

Abstract: A method of manufacturing a resin multilayer substrate is provided in which a component (3) is incorporated in a stacked body obtained by stacking a plurality of thermoplastic resin sheets (2). The method includes the steps of: softening a first resin sheet (2a) by heating, and pressing the component (3) against the first resin sheet (2a), thereby fixing the component (3) to the first resin sheet (2a); stacking the first resin sheet (2a) on a second resin sheet (2b) having a through hole (14) receiving the component (3) and a third resin sheet (2c) located adjacent to a lower side of the component (3) such that the component (3) is inserted into the through hole (14) and the lower surface of the component (3) faces the third resin sheet (2c); and performing compression bonding by heating and pressurizing the stacked body including these resin sheets (2).

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A substrate (3) in which a through-hole (2) is filled with a filler (4) is prepared, and a structure (6), at least a part of the surface of which has an insulating property, is formed on the surface of the substrate (3). A plated layer (7) is formed on the substrate (3) having the structure (6) formed thereon, and the filler (4) and the structure (6) are removed. Thus, a through-hole substrate (8) is formed, in which the plated layer (7) having an opening (9) communicating with the through-hole (2) is provided on at least one surface of a substrate (1).

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.

Abstract: A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening.

Abstract: A semiconductor device and a fabricating process for the same are provided. The semiconductor device includes a base layer having a part of a reactive material; and a self-assembled protecting layer of a self-assembled molecule reacting with the reactive material formed over the part.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

Abstract: A interconnect structure includes a conductive layer formed in a dielectric layer. An adhesion layer is formed between the dielectric layer and a substrate. The adhesion layer has a carbon content ratio greater than a carbon content ratio of the dielectric layer.

Abstract: A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH2)n—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen, a high frequency radio frequency power in a PECVD chamber and an energy post treatment including ultraviolet radiation. An ultra low k porous SiCOH dielectric material having at least one of a k in the range from 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, and 2.5 to 2.55 and a modulus of elasticity greater than 5, 6, 7.8 and 9 GPa, respectively and a semiconductor integrated circuit comprising interconnect wiring having porous SiCOH dielectric material as described above.

Abstract: An insulating material interposed between two conductive materials can experience plasma process induced damage (PPID) when a plasma process is used to deposit a dielectric onto one of the conductive materials. This PPID can be reduced by reducing electric charge accumulation on the one conductive material during the plasma process dielectric deposition.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: Methods for substrate processing are described. The methods include forming a material layer on a substrate. The methods include selecting constituents of a molecular masking layer (MML) to remove an effect of variations in the material layer as a result of substrate processing. The methods include normalizing the surface characteristics of the material layer by selectively depositing the MML on the material layer.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias.

Abstract: A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits.

Abstract: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

Abstract: A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Abstract: A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 ?m and an interlayer disposed in the multilayer metallization with a first side of the interlayer adjoining one layer of the multilayer metallization and a second opposing side of the interlayer adjoining a different layer of the multilayer metallization. The interlayer includes at least one of W, WTi, Ta, TaN, TiW, and TiN or other suitable compound metal or a metal silicide such as WSi, MoSi, TiSi, and TaSi.

Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.

Abstract: A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs.

Abstract: A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.

Abstract: A hybrid photo-patternable dielectric material is provided that has dual-tone properties with a parabola like dissolution response to radiation. In one embodiment, the hybrid photo-patternable dielectric material includes a composition of at least one positive-tone component including a positive-tone polymer, positive-tone copolymer, or blends of positive-tone polymers and/or positive-tone copolymers having one or more acid sensitive positive-tone functional groups; at least one negative-tone component including a negative-tone polymer, negative-tone copolymer, or blends of negative-tone polymers and/or negative-tone copolymers having one or more acid sensitive negative-tone functional groups; at least one photoacid generator; and at least one solvent that is compatible with the positive-tone and negative-tone components.

Abstract: Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein employ additional processing to ensure pitch divided lines have the spatial isolation necessary to prevent shorting problems. The pitch division techniques described herein further employ processing acts to increase the structural robustness of high aspect ratio features.

Abstract: A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.

Abstract: In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.

Abstract: A semiconductor device is provided, which includes a first insulating layer over a first substrate, a transistor over the first insulating layer, a second insulating layer over the transistor, a first conductive layer connected to a source region or a drain region of the transistor through an opening provided in the second insulating layer, a third insulating layer over the first conductive layer, and a second substrate over the third insulating layer. The transistor comprises a semiconductor layer, a second conductive layer, and a fourth insulating layer provided between the semiconductor layer and the second conductive layer. One or plural layers selected from the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer have a step portion which is provided so as not to overlap with the transistor.

Abstract: An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas.

Abstract: A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

Abstract: A multi-layered metal interconnection includes a diffusion barrier directly formed on a conductive layer, an etching stop layer directly formed on the diffusion barrier, at least one dielectric layer formed over the etch stop layer, at least one of a via formed in the at least one dielectric layer and a trench formed in the at least one dielectric layer.