Abstract: A semiconductor device including a semiconductor substrate; a memory cell structure on the semiconductor substrate; and a peripheral wiring structure between the semiconductor substrate and the memory cell structure to connect the semiconductor substrate and the memory cell structure, wherein the peripheral wiring structure includes at least one lower wiring structure and an upper wiring structure on the at least one lower wiring structure, the at least one lower wiring structure includes a lower wiring, the upper wiring structure includes an upper wiring, the lower wiring includes a first material layer having first grains, the upper wiring includes a second material layer having second grains, an average size of the second grains is smaller than an average size of the first grains.

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

Abstract: A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof.

Abstract: The laminated high melting point soldering layer includes: a laminated structure which laminated a plurality of three-layered structures, the respective three-layered structures including a low melting point metal thin film layer and a high melting point metal thin film layers disposed on a surface and a back side surface of the low melting point metal thin film layer; a first high melting point metal layer disposed on the surface of the laminated structure; and a second high melting point metal layer disposed on the back side surface of the laminated structure. The low melting point metal thin film layer and the high melting point metal thin film layer are mutually alloyed by TLP, and the laminated structure, and the first high melting point metal layer and the second high melting point metal layer are mutually alloyed by the TLP bonding.

Abstract: A titanium-nickel-palladium solderable metal system for silicon power semiconductor devices (10), which may be used for one or both of the anode (20) or cathode (30). The metal system includes an outer layer of palladium (40,70), an intermediate layer of nickel (50,80), and an inner layer of titanium (60,90). For certain applications, the nickel may be alloyed with vanadium. The metal system may be deposited on bare silicon (100) or on one or more additional layers of metal (110) which may include aluminum, aluminum having approximately 1% silicon, or metal silicide. The use of palladium, rather than gold or silver, reduces cost, corrosion, and scratching.

Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: The laminated high melting point soldering layer includes: a laminated structure which laminated a plurality of three-layered structures, the respective three-layered structures including a low melting point metal thin film layer and a high melting point metal thin film layers disposed on a surface and a back side surface of the low melting point metal thin film layer; a first high melting point metal layer disposed on the surface of the laminated structure; and a second high melting point metal layer disposed on the back side surface of the laminated structure. The low melting point metal thin film layer and the high melting point metal thin film layer are mutually alloyed by TLP, and the laminated structure, and the first high melting point metal layer and the second high melting point metal layer are mutually alloyed by the TLP bonding.

Abstract: In accordance with the invention, there are diffusion barriers, integrated circuits, and semiconductor devices and methods of fabricating them. The method of fabricating a diffusion barrier can include providing a dielectric layer, forming a first silicon enriched layer over the dielectric layer by exposing the dielectric layer to a silicon-containing ambient, and forming a barrier layer over the first silicon enriched layer.

Abstract: A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer.

Abstract: The invention provides a wireless chip which can secure the safety of consumers while being small in size, favorable in communication property, and inexpensive, and the invention also provides an application thereof. Further, the invention provides a wireless chip which can be recycled after being used for managing the manufacture, circulation, and retail. A wireless chip includes a layer including a semiconductor element, and an antenna. The antenna includes a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer, and has a spherical shape, an ovoid shape, an oval spherical shape like a go stone, an oval spherical shape like a rugby ball, or a disc shape, or has a cylindrical shape or a polygonal prism shape in which an outer edge portion thereof has a curved surface.

Abstract: A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.

Abstract: A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

Abstract: There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract: A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: A semiconductor device includes a semiconductor chip; and a scribe line disposed in an adjacent way to and around the semiconductor chip. The scribe line comprises an interlayer insulating film and an accessory. The accessory comprises a first portion with a layer shape formed on the interlayer insulating film and a second portion extending downward from the first portion into the interlayer insulating film in a thickness direction thereof.

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.

Abstract: A method for manufacturing an integrated circuit structure is disclosed. First, a dielectric layer is formed on a substrate, the substrate has a transistor region and a diode region. Next, a contact hole and an opening are formed in the dielectric layer, a size of the opening being larger than that of the contact hole. Nest, a first metal layer is formed on the dielectric layer and filled into the contact hole and the opening. Next, a portion of the first metal layer is removed to form a contact plug above the transistor region and form a metal spacer on a sidewall of the opening. Next, an ion implantation process is performed to form a lightly doped region in the substrate at a bottom of the opening. Finally, a contact metal layer is formed on the lightly doped region.

Abstract: An etching stopper film is formed on top of a first insulating film. The etching stopper film is a film formed by depositing at least two films, made of constituent materials identical in quality to each other, one another. Subsequently, a first opening pattern is formed in the etching stopper film. Subsequently, a second insulating film is formed on top of the etching stopper film. Subsequently, a mask pattern is formed on top of the second insulating film. Subsequently, the second insulating film is etched with the use of the mask pattern as a mask to be followed by etching of the first insulating film with the use of the etching stopper film as a mask.

Abstract: Semiconductor fabricating technology is provided, and particularly, a method of fabricating a semiconductor device improving a contact characteristic between a silicon layer including carbon and a metal layer during a process of fabricating a semiconductor device is provided. A semiconductor device including the silicon layer including carbon and the metal layer formed on the silicon layer is provided. A metal silicide layer is interposed between the silicon layer including carbon and the metal layer.

Abstract: An interconnection structure for a semiconductor device may include lower interconnection patterns disposed in a checker board shape and upper interconnection patterns disposed in a checker board shape and connecting two adjacent lower interconnection patterns to each other.

Abstract: A semiconductor device, may include a first insulating layer formed on a semiconductor substrate, a contact provided in the first insulating layer, a second dielectric layer formed on the first insulating layer, the second insulating layer having lower dielectric constant than the first dielectric layer, a wiring formed in the second insulating layer and being electrically connected to the contact, a first barrier metal formed on a bottom of the contact and on a side surface of the wiring, and a second barrier metal formed on a side surface of the bottom and on the first barrier metal.

Abstract: An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track 8 can be formed with a stopper 16 which can be positioned at least at one end of the electrically conductive track 8. The differential expansion during heating of electrically conductive tracks 8 with respect to a semiconductor wafer 4 can be restricted by the stopper 16.

Abstract: Methods for forming conductive vias include foiling one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof A barrier layer may be fowled over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

Abstract: A semiconductor device includes: a trench formed on an interlayer insulating film on a semiconductor substrate; a first barrier metal film formed to cover the bottom and sidewalls of the trench, the first barrier metal film being comprised of an electric conductor containing a platinum-group element, a refractory metal, and nitrogen; and a metal film formed on the first barrier metal film in the trench. The amount of nitrogen decreases in the thickness direction of the first barrier metal film toward the metal film.

Abstract: At least part of an element isolation region, an interlayer insulating film, and a protection insulating film, other than a gate insulating film (silicon oxide film), is formed of carbon fluoride (CFx, 0.3<x<0.6) or hydrocarbon (CHy, 0.8<y<1.2).

Abstract: Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the like.

Abstract: An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

Abstract: A method for manufacturing a semiconductor device, includes: mounting a semiconductor chip having an electrode on a wiring substrate having a base substrate and a wiring formed on the base substrate; forming a eutectic alloy by contacting the wiring with the electrode and by heating and pressurizing, and; forming the eutectic alloy so as a part of the eutectic alloy enters between the wiring and the base substrate.

Abstract: A joint structure joins an electronic element 12 included in an electronic component to an electrode 14 included in that electronic component. The joint structure includes a solder layer, which contains 0.2 to 6% by weight of copper, 0.02 to 0.2% by weight of germanium and 93.8 to 99.78% by weight of bismuth, a nickel layer provided between the solder layer and the electrode, and a barrier layer provided between the nickel layer and the solder layer. Here, the barrier layer is formed so as to have an average thickness of from 0.5 to 4.5 ?m after the electronic element and the electrode are joined by the solder layer.

Abstract: The present invention relates to a substrate notably designed to enter into the constitution of a solar cell, of which one face, called the inner face, is designed to receive a molybdenum-based conductive element. This substrate is characterized in that the conductive element is formed of several layers based on molybdenum, at least one of these layers being enriched with molybdenum oxide. The present invention also relates to solar cells employing such a substrate and a method for producing same.

Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.

Abstract: A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive wiring.

Abstract: An integrated circuit package has a substrate; a discrete capacitor coupled to a first surface of the substrate; an integrated circuit die coupled to the first surface of the substrate over the discrete capacitor; and a lid coupled to the substrate, the lid encapsulating the integrated circuit die and the discrete capacitor.

Abstract: A semiconductor nanowire is coated with a chemical coating layer that comprises a functional material which modulates the quantity of free charge carriers within the semiconductor nanowire. The outer surface of the chemical coating layer includes a chemical group that facilitates bonding with molecules to be detected through electrostatic forces. The bonding between the chemical coating layer and the molecules alters the electrical charge distribution in the chemical coating layer, which alters the amount of the free charge carriers and the conductivity in the semiconductor nanowire. The coated semiconductor nanowire may be employed as a chemical sensor for the type of chemicals that bonds with the functional material in the chemical coating layer. Detection of such chemicals may indicate pH of a solution, a vapor pressure of a reactive material in gas phase, and/or a concentration of a molecule in a solution.

Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming (101) desired device regions (21) with contacts (22) on the front surface (19) of an initially relatively thick wafer (18?); etching (104) via cavities (29) partly through the wafer (18?) in the desired locations; filling (105) the via cavities (29) with a conductive material (32) coupled to some device region contacts (22); mounting (106) the wafer (18?) with its front side (35) facing a support structure (40); thinning (107) the wafer (18?) from the back side (181) to expose internal ends (3210, 3220, 3230, 3240, etc.) of the conductive material filled vias (321, 322, 323, 324, etc.); applying (108) any desired back-side interconnect region (44) coupled to the exposed ends (3210, 3220, 3230, 3240, etc.

Abstract: One or more embodiments of the present invention relate to structures obtained by methods (a) for growing a film by an intermixing growth process, or (b) by depositing a film, which film includes chalcogenides of copper and/or silver (but excluding oxides), such as, for example, copper sulfide (CuSX and/or Cu2SX, where 0.7?X?1.3; and X=1.0 for stoichiometric compounds).

Abstract: A semiconductor device according to one embodiment includes: a semiconductor element formed on a semiconductor substrate; a metal wiring formed above the semiconductor element; an amorphous silicon film formed above the semiconductor element, the amorphous silicon film being insulated from the metal wiring; and a metal diffusion blocking film formed above the amorphous silicon film, the metal diffusion blocking film having a property to suppress diffusion of metal atoms in the metal wiring.

Abstract: The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer (108) of a first dielectric material is deposited on an exposed surface (102.1) of the interconnect element. Susequently, particles (110) are implanted into the first dielectric layer and the interconnect element (102) so as to let the interconnect material mix with the first dielectric material in a first interface region (102.2) between the interconnect element and the first dielectric layer.

Abstract: Provided is an amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed low dielectric constant, a semiconductor device including the amorphous carbon film and a technology for forming the amorphous carbon film. Since the amorphous carbon film is formed by controlling an additive amount of Si (silicon) during film formation, it is possible to form the amorphous carbon film having a high elastic modulus and a low thermal contraction rate with a suppressed dielectric constant as low as 3.3 or less. Accordingly, when the amorphous carbon film is used as a film in the semiconductor device, troubles such as a film peeling can be suppressed.

Abstract: The present invention relates to a very thin multilayer diffusion barrier for a semiconductor device and fabrication method thereof. The multilayer diffusion barrier according to the present invention is fabricated by forming a very thin, multilayer diffusion barrier composed of even thinner sub-layers, where the sub-layers are only a few atoms thick. The present invention provides a diffusion barrier layer for a semiconductor device which is in a substantially amorphous state and thermodynamically stable, even at high temperatures.

Abstract: An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings.

Abstract: There are provided a method of forming a fine metal pattern and a method of forming a metal line using the same. In the method of forming a fine metal pattern, a substrate is prepared where a first interlayer insulating layer is formed. A via plug is formed on the first interlayer insulating layer. A plurality of sidewall buffer patterns are formed on the first interlayer insulating layer having the via plug, wherein the plurality of the sidewall buffer patterns are spaced apart from each other by a predetermined distance. The sidewall layer is deposited on the first interlayer insulating layer and the sidewall buffer patterns. The sidewall layer is etched such that sidewall patterns remains on sidewalls of the sidewall buffer patterns.

Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.

Abstract: The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.

Abstract: An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.