Abstract: A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body includes a plurality of layer portions stacked. In a method of manufacturing the layered chip package, a plurality of structures are initially formed. Each structure includes at least one main-body-forming portion that is to be the main body and that has a pre-wiring surface. Next, the plurality of structures are surrounded with a jig and thereby aligned so that their pre-wiring surfaces face upward. The jig has a top surface that is lower in level than the pre-wiring surfaces. Next, a resin layer covering the jig and the structures is formed using a resin film. Next, the resin layer is polished until the pre-wiring surfaces are exposed. Next, the wiring is formed on the pre-wiring surfaces simultaneously. Next, the main-body-forming portions are separated from each other.

Abstract: An electrically optimized and structurally protected micro via structure for high speed signals in multilayer interconnection substrates is provided. The via structure eliminates the overlap of a contact with the reference planes to thereby reduce the via capacitance and thus, the via impedance mismatch in the via structure. As a result, the via structure is electrically optimized. The via structure further comprises one or more floating support members placed in close proximity to the via within a via clearance area between the via and the reference planes. The floating support members are “floating” in the sense that they are not in electrical contact with either the via or the reference planes. Thus, they are not provided for purposes of signal propagation but only for structural support. The floating support members may be connected to one another by way of one or more microvia structures.

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.

Abstract: The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).

Abstract: A multilayer substrate includes an insulating base member having a plurality of resin films, an electric element embedded in the insulating base member, and a spacer. The resin films are made of a thermoplastic resin and stacked and attached to each other. At least one resin film has a through hole for inserting the electric element. The one resin film further has a plurality of protruding members. One protruding member opposes to another one protruding member so that the one and the another one contact and sandwich the electric element. The spacer is arranged between the one resin film and an adjacent resin film and is disposed at a base portion of one of the protruding members.

Abstract: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.

Abstract: To provide a manufacturing method of a semiconductor device in which manufacturing cost can be reduced, and a manufacturing method of a semiconductor device with reduced manufacturing time and improved yield. A manufacturing method of a semiconductor device is provided, which includes the steps of forming a first layer containing a metal over a substrate, forming a second layer containing an inorganic material on the first layer, forming a third layer including a thin film transistor on the second layer, irradiating the first layer, the second layer, and the third layer with laser light to form an opening portion through at least the second layer and the third layer.

Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.

Abstract: A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode.

Abstract: The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the formation of lighting devices including, but not limited to, LED devices, High Brightness (HB) LED backlights, display-related light sources, automotive lighting, decorative lighting, signage and advertisement lighting, and information display lighting.

Abstract: An IC chip for a high frequency region, particularly, a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer is formed at a thickness of 30 ?m on a core substrate and a conductive circuit on an interlayer resin insulation layer is formed at a thickness of 15 ?m. By thickening the conductive layer, the volume of the conductor itself can be increased thereby decreasing its resistance. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

Abstract: A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

Abstract: A first multilayer wiring structural body 16 and a second multilayer wiring structural body 56 are simultaneously formed on both surfaces 101A, 101B of a substrate 101 and thereafter the portion of a structural body 120 corresponding to a third region C1 is folded so as to oppose a second structural body 22 to a second structural body 62 and the first multilayer wiring structural body 16 is electrically connected to the second multilayer wiring structural body 56.

Abstract: A multi-chip device can have a plurality of chips in a stair-step arrangement having respective chip pads thereon. A mold packaging material encapsulates the plurality of chips and at least one conductive via, that is in the mold packaging material and extends from an outer surface of the material, contacts a respective one of the chip pads. A conductive material is in the at least one conductive via.

Abstract: A bonded substrate comprising two semiconductor substrates is provided. Each semiconductor substrate includes semiconductor devices. At least one through substrate via is provided between the two semiconductor substrates to provide a signal path therebetween. The bottom sides of the two semiconductor substrate are bonded by at least one bonding material layer that contains a cooling mechanism. In one embodiment, the cooling mechanism is a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. In another embodiment, the cooling mechanism is a conductive cooling fin with two end portions and a contiguous path therebetween. The cooling fin is connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.

Abstract: A semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layer of the intermediate layer. The support is made of a deposited material that has a lower quality than that of one or both of the intermediate and useful layers. A bonding layer may be included on one of the intermediate layer or the useful layer, or both, to facilitate bonding of the layers an a thin layer may be provided between the useful layer and intermediate layer. These final substrates are useful in optic, electronic, or optoelectronic applications.

Abstract: An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.

Abstract: A semiconductor device is provided that includes one or more ceramic material layers and one or more low dielectric constant (low-K) epoxy layers on top to be electrically coupled to an integrated circuit device, such as a chip die. The resulting ceramic/organic hybrid substrate takes advantage of the thin low-cost, low-K epoxy layer, by routing the dense circuitry from the chip die to the ceramic material layer. In addition, the use of low-K epoxy layer may reduce the number of ceramic material layers required to about three layers, thus significantly reducing the cost of the substrate. Low-K epoxy material layer may be laminated onto the ceramic material layer to reduce throughput time and cost. The ceramic/organic hybrid substrate may also take advantage of the properties of ceramic materials, which have a much more rigid structure than organic materials and a low CTE (coefficient of thermal expansion) that works well with ultra low-K chip dies.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A method of fabricating composite substrates by associating a transfer layer with an intermediate support to form an intermediate substrate of predetermined thickness with the transfer layer having a free surface; providing a sample carrier having a surface and a recess that has a depth that is approximate the same as the predetermined thickness of the intermediate substrate so that the transfer layer free surface is positioned flush with the sample carrier surface; providing a support layer both on the transfer layer free surface and on a portion of the sample carrier surface surrounding the recess; removing the portion of the support layer that extends beyond the intermediate substrate; and detaching the transfer layer and support layer from its intermediate support to form the composite substrate. The support layer is made of a deposited material that has a lower quality than that of the intermediate support.

Abstract: A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: This invention discloses an I/O pad structure in an integrated circuit (IC) which comprises a first vertical region in the IC including a top metal layer and one or more semiconductor devices formed thereunder, the top metal layer in the first vertical region serving as a first pad, the semiconductor devices being electrically connected to the first pad, and a second vertical region in the IC next to the first vertical region including the top metal layer and one or more through-silicon-vias (TSVs) formed thereunder, the top metal layer in the second vertical region serving as a second pad, and no semiconductor devices being formed beneath the second pad, the TSVs being electrically connected to the second pad, wherein the first and the second pad are electrically connected through at least one metal layer.

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region.

Abstract: A method for measuring the thickness of a layer is provided, comprising (a) providing a structure (101) comprising a first layer disposed on a second layer; (b) impinging (103) the structure with a first ion beam comprising a first isotope, thereby sputtering off a portion of the first layer which contains a second isotope and exposing a portion of the second layer; and (c) determining (105) the thickness of the first layer by measuring the amount of the second isotope which is sputtered off.

Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.

Abstract: A chip assembly includes a semiconductor chip and a wirebonded wire. The semiconductor chip includes a passivation layer over a silicon substrate and over a thin metal structure, a first thick metal layer over the passivation layer and on a contact point of the thin metal structure exposed by an opening in the passivation layer, a polymer layer over the passivation layer and on the first thick metal layer, and a second thick metal layer on the polymer layer and on the first thick metal layer exposed by an opening in the polymer layer. The first thick metal layer includes a copper layer with a thickness between 3 and 25 micrometers. The wirebonded wire is bonded to the second thick metal layer.

Abstract: A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads.

Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip. The first-type semiconductor chip includes a plurality of memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading on and from the memory cells included in the plurality of first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the main body and connected to the wiring.

Abstract: A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and the insulating film to react with each other, thereby forming an insulative barrier film mainly comprising a compound of the predetermined metallic element and a constituent element of the insulating film in a self-aligned manner at a boundary surface between the precursor film and the insulating film, removing an unreacted part of the precursor film after forming the barrier film, forming a conductive film comprising at least one of Ru and Co on the barrier film, depositing a wiring material film on the conductive film, and forming a wiring from the wiring material film to provide a wiring structure.

Abstract: There is provided a wiring substrate. The wiring substrate includes a wiring member and a reinforcing layer. The wiring member is formed by layering insulating layers and wiring layers and has connection pads thereon. The reinforcing layer is provided on the wiring member to surround the connection pads and has a plurality of concave-convex portions thereon.

Abstract: A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed.

Abstract: The invention relates to a method for applying rewiring to a panel. For this purpose, a panel is provided which has a coplanar overall upper side of an upper side of a plastic compound and the upper sides of semiconductor chips. The method provides a rewiring layer with implementation of external contacts and rewiring lines which, by means of a two-stage exposure step, compensates for position errors of the semiconductor chips in the component positions of the panel.

Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract: A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line.

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: The present disclosure relates to an integrated circuit packaging, a strip having a plurality of integrated circuit packages, and method of manufacture thereof, and more particularly, to a substrate having an integrated overhang support structure to support a ledge created by stacking a large circuit die on a small circuit die. In one embodiment, the upper substrate surface comprises a protrusion as an integrated support structure. The structure may include passages to direct the flow of underfill into the limited support area to create an open area for vacuum or for placement of passive or active components.

Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.

Abstract: A semiconductor substrate that includes a relatively thin monocrystalline useful layer, an intermediate layer transferred from a source substrate, and a relatively thick layer of a support present on one of the useful layer of the intermediate layer. The support is made of a deposited material that has a lower quality than that of one or both of the intermediate and useful layers. A bonding layer may be included on one of the intermediate layer or the useful layer, or both, to facilitate bonding of the layers an a thin layer may be provided between the useful layer and intermediate layer. These final substrates are useful in optic, electronic, or optoelectronic applications.

Abstract: A semiconductor device is provided which can suppress the deterioration of its reliability caused by liquid soaking into a gap. The semiconductor device includes plural gate electrode layers and an interlayer insulating film. The gate electrode layers are formed so as to extend in the same direction in a planar layout and each have a gate wiring portion and a contact pad portion. The interlayer insulating film is formed over the gate electrode layers and gaps so as to leave the gaps each between adjacent gate wiring portions and also between adjacent gate wiring portion and contact pad portion. A second spacing which is the distance between adjacent gate wiring portion and contact pad portion is 2.1 times or less as large as a first spacing which is the distance between adjacent gate wiring portions.

Abstract: A circuit board has a metal pattern that is formed on a surface of the circuit board to be connected with bumps in two-dimensional arrangement for mounting an electronic device that has the bumps. A plurality of the bumps which has even electrical potentials is electrically connected by the metal pattern on the surface of the circuit pattern.

Abstract: In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the substrate to allow heat to be conducted away from the backside of the die to a top most metal layer of the substrate. Thermal balls may be attached to the bottom side of the substrate on the same plane as the die.