Abstract: This application provides a stiffener ring and a surface packaging assembly. The stiffener ring is configured to correct warpage of a substrate of the surface packaging assembly. The stiffener ring includes an annular stiffener ring body and an adjustment block that is disposed at a same layer as the stiffener ring body and that is fastened to at least one corner of the stiffener ring body. A coefficient of thermal expansion of the adjustment block is less than a coefficient of thermal expansion of the stiffener ring body. Coordination between the adjustment block and the stiffener ring body alleviates an “M-shape” overpressure phenomenon of a warpage deformation caused by the stiffener ring to the substrate at a high temperature, reduces warpage of the substrate, and improves flatness of the surface packaging assembly.

Abstract: A printed circuit board includes a first substrate portion including a plurality of first insulating layers, a plurality of first wiring layers respectively disposed on the plurality of first insulating layers, and a plurality of first adhesive layers respectively disposed between the plurality of first insulating layers to respectively cover the plurality of first wiring layers; and a second substrate portion disposed on the first substrate portion, and including a plurality of second insulating layers, a plurality of second wiring layers respectively disposed on the plurality of second insulating layers, and a plurality of second adhesive layers respectively disposed between the plurality of second insulating layers to respectively cover the plurality of second wiring layers.

Abstract: A thermalization structure is formed using a cover configured with a set of pillars, the cover being a part of a cryogenic enclosure of a low temperature device (LTD). A chip including the LTD is configured with a set of cavities, a cavity in the set of cavities having a cavity profile. A pillar from the set of pillars and corresponding to the cavity has a pillar profile such that the pillar profile causes the pillar to couple with the cavity of the cavity profile within a gap tolerance to thermally couple the chip to the cover for heat dissipation in a cryogenic operation of the chip.

Abstract: A semiconductor package structure includes a substrate, including first conductive pads and packaging pads opposite to the first conductive pads, one or more semiconductor chips stacking on the substrate, a molding compound encapsulating the semiconductor chips, first metal wires connecting the semiconductor chips to the packaging pads, a first metal pad on a side of the molding compound opposite to the substrate, and a second metal wire located in the molding compound and connecting the first metal pad to a chip-contact pad of a semiconductor chip of the semiconductor chips.

Abstract: The present invention provides a metal interconnection structure and a manufacturing method thereof, the metal interconnection structure includes: metal interconnection lines disposed at intervals, first metal layers respectively disposed on the metal interconnection lines; second metal layers respectively disposed on the first metal layers; dielectric layers disposed on both sides of the first metal layer and the second metal layer and having a gap with both the first metal layer and the second metal layer; and a metal diffusion covering layer covering the dielectric layer and the second metal layer.

Abstract: Described herein are circuit assemblies comprising flexible interconnect circuits and/or other components connected to these circuits. In some examples, conductive elements of different circuits are connected with support structures, such as rivets. Furthermore, conductive elements of the same circuit can be interconnected. In some examples, a conductive element of a circuit is connected to a printed circuit board (or other devices) using a conductor joining structure. Interconnecting different circuits involves stacking these circuits such that the conductive element in one circuit overlaps with the conductive element in another circuit. A support structure protrudes through both conductive elements and any other components positioned in between, such as dielectric and/or adhesive layers. This structure electrically connects the conductive elements and also compresses the conductive elements toward each other. For example, a rivet is used with the rivet heads contacting one or two conductive elements, e.g.

Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Abstract: A camera may include a printed circuit board (PCB) that may include at least one coil and at least one position sensor. The coil may be embedded at least partially inside the PCB at a first side of the PCB, whilst the position sensor may be attached to the PCB at a second side opposite the first side. The PCB may include an aperture through the PCB at a location corresponding to the position sensor to enhance sensing of the position sensor. The PCB may further include at least one recess inside which the position sensor may be attached to the PCB.

Abstract: An electronic device includes a carrier having at least one bonding pad, a plurality of electronic elements disposed on the carrier and one of the electronic elements including a substrate and at least one connecting terminal disposed between the substrate and the carrier. The electronic elements are electrically connected to the at least one bonding pad via the at least one connecting terminal.

Abstract: An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described.

Abstract: The laminate of the present disclosure includes multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. The B concentration of a surface layer portion of the laminate is lower than the B concentration of an inner layer portion of the laminate.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked structure in which a plurality of conductive layers is stacked in a stacking direction via an insulating layer, a plurality of pillars extending in the stacking direction in the stacked structure and including a memory cell formed at an intersection between at least a part of the plurality of conductive layers and at least a part of the plurality of pillars, a plurality of first contacts arranged in the stacked structure, each of the first contacts reaching a different depth in the stacked structure and being connected to a conductive layer in a different layer among the plurality of conductive layers, and a plurality of second contacts arranged in the stacked structure separately from the plurality of first contacts, each of the second contacts being connected to a conductive layer identical to the conductive layer to which corresponding one of the plurality of first contacts is connected.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.

Abstract: A flexible printed circuit board which includes: a base film; and multiple wires formed on the base film, in which in a region attached to a battery including multiple arrayed cells, a conductor portion to be the multiple wires is provided only on one surface of the base film, at at least part of a region apart from the region attached to the battery, a conductor portion to be the multiple wires is provided on each surface of the base film, and the flexible printed circuit board further includes multiple conductive portions configured to electrically connect the wires on one surface side of the base film and the wires on the other surface side of the base film.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.

Abstract: A packaging method includes providing a substrate structure, including a core substrate, a plurality of first conductive pads at a first surface of the core substrate, and a plurality of packaging pads at a second surface of the core substrate; and packaging a plurality of semiconductor chips onto the substrate structure at the second surface of the core substrate, including forming a first metal wire to connect with a chip-contact pad of a semiconductor chip, and forming a molding compound on the second surface of the core substrate to encapsulate the plurality of semiconductor chips. One end of the first metal wire connects to the chip-contact pad, and another end of the first metal wire is exposed at the surface of the molding compound. The packaging method further includes forming a first metal pad on the surface of the molding compound to electrically connect with the first metal wire.

Abstract: An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

Abstract: A ceramic substrate of the present disclosure is a ceramic substrate including a ceramic body having a ceramic layer on a surface thereof and a surface electrode placed on a primary face of the ceramic body. Between the surface electrode and the ceramic layer is an oxide layer made of an insulating oxide having a melting point higher than the firing temperature for the ceramic layer. The oxide layer also extends on the ceramic layer not occupied by the surface electrode. The oxide layer on the ceramic layer not occupied by the surface electrode has a rough surface.

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

Abstract: Various deficiencies in the prior art are addressed by systems, methods, architectures, mechanisms and/or apparatus configured for fabricating a strain sensing device directly on a structure by printing or otherwise depositing a material on the structure, the material exhibiting a piezo-resistive effect, and sintering a strain sensing pattern from the material such that the strain sensing pattern becomes electrically conductive.

Abstract: A method of manufacturing a component carrier includes forming a stack with electrically conductive layer structures and at least one electrically insulating layer structure; configuring the stack as a redistribution structure for transferring between a smaller pitch on one side of the stack towards a larger pitch on an opposing other side of the stack; arranging a first stiffening structure and a second stiffening structure in opposing surface regions of the stack. A component carrier and an electric device manufactured with the method exhibit improved stiffness and signal integrity.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: A circuit assembly where the circuit board includes a first surface and a second surface that is opposite to the first surface and on which a plurality of bus bars are routed, the inductor includes a main body and a terminal that is led out from the main body and has a shape that is bent toward the circuit board, and a leading end of the terminal is connected through a screwing member to a bus bar of the plurality of bus bars exposed from an opening provided on the circuit board, the screwing member is held in an insulating holder housed in a housing recess provided in the heat dissipation plate, and the heat dissipation plate is overlaid so as to transfer heat on the circuit board on the second surface of the circuit board.

Abstract: An electronic system for identifying an article can include a printed memory having a plurality of contact pads electrically coupled to a plurality of landing pads positioned on a first side of a printed circuit board (PCB) substrate. The plurality of landing pads can be electrically coupled to a plurality of endless, concentric contact lines positioned on a second side of the PCB substrate through a plurality of vias that extend through a thickness of the PCB substrate and a plurality of traces that electrically couple the plurality of vias with the plurality of landing pads. To perform a memory operation on the printed memory, contact probes of a reader are physically and electrically contacted with the plurality of concentric contact lines. In some implementations, the memory operation can be performed on the printed memory irrespective of a rotational orientation of the printed memory relative to the reader.

Abstract: A flexible substrate and a flexible display device including the same are disclosed. In one aspect, the flexible substrate includes a first substrate that is flexible and a metal wiring layer over the first substrate and having a first surface facing the first substrate, a second surface opposite to the first surface, and a plurality of holes penetrating the first and second surfaces. The holes are arranged in a plurality of rows. The holes comprise a first hole in an n-th row and a first hole in a (n?1)th row. The first hole of the n-th row is spaced apart from the first hole in the (n?1)th row by a first distance, and an edge of each of the holes is curved.

Abstract: In an exemplary embodiment, a passive component which is a surface mounting component, includes: a substrate body 10 having insulation property; an internal conductor 50 embedded in the substrate body 10; and an external electrode 70 provided on the bottom face 12, which is the mounting surface, of the substrate body 10 and electrically connected to the internal conductor 50; wherein the external electrode 70 has a face 86 roughly parallel with the bottom face 12 of the substrate body 10, and a dome-shaped projection 80 that bulges, with reference to the roughly parallel face 86, away from the bottom face 12 of the substrate body 10. The passive component can prevent misalignment problems at mounting.

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Abstract: An electrical interconnect assembly includes an insulating substrate, upper conductive pads coupled to a top surface of the insulating substrate, and lower conductive pads coupled to a bottom surface of the insulating substrate. The upper conductive pads and the lower conductive pads comprise an electrically conductive material. A metallization layer is deposited on the top surface of the insulating substrate and the upper conductive pads. The metallization layer extends through vias formed through a thickness of the insulating substrate to contact a top surface of the lower conductive pads.

Abstract: Printed circuit boards (PCBs) can be designed to have dynamic warp characteristics complimentary to those of an attached component. A PCB and an attached component can be designed to dynamically warp, during a thermal excursion, in the same direction and with approximately the same magnitude of warp. Warp characteristics of the PCB and the attached component can be determined by the vertical thickness of conductor and dielectric layers, by the wiring density and number of conductor layers. Warp characteristics can also be at least partially determined by the arrangement/ordering of conductor and dielectric layers, by dimensions of a sash structure surrounding a component outline and by dimensions of a prepreg layer applied to an existing design. Such a prepreg layer can cover a portion or an entirety of one of the PCBs planar surfaces.

Abstract: In one embodiment, a method for forming an embedded trace substrate includes forming a conductive layer on a carrier. A dielectric film is provided on the conductive layer. Vias are formed in the dielectric film and extend to portions of the conductive layer. A conductive pattern is formed on the dielectric layer and is electrically connected to the conductive layer through the vias. The carrier is removed and portions of the conductive layer are selectively removed to provide a plurality of bumps pads configured to protrude outwardly from the dielectric layer.

Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract: A semiconductor device or semiconductor device package for transmitting a plurality of differential signals, the reliability of which hardly deteriorates. The semiconductor device is an area array semiconductor device in which a plurality of lands (external terminals) including a plurality of lands for transmitting a plurality of differential signals are arrayed in a matrix pattern in the back surface of a wiring substrate. Some of the lands are located in the outermost periphery of the matrix pattern. Some others of the lands are located inward of the outermost periphery of the matrix pattern and in rows next to the outermost periphery. The spacing between lands in a second region between the lands located in the rows next to the outermost periphery and the side surface of the wiring substrate is larger than in a first region in the outermost periphery.

Abstract: A package body (1) with an upper side (2), with an underside (22), opposite from the upper side (2), and with a side surface, which connects the upper side (2) and the underside (22) and is provided as a mounting surface (19), the package body (1) having a plurality of layers (8) which contain a ceramic material, and a main direction of extent of the layers (23, 24, 25) running obliquely in relation to the mounting surface (19). Furthermore, a method for producing a package body (1) is provided.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

Abstract: A method of processing a wafer includes establishing a fine of symmetry defining left and right die areas on a front side of the wafer and left and right die areas on a back side. A first mask is used to form a first interconnection layer on the left and right die areas comprising a first portion on the left die area and second portion different than the first portion on the right die area. A second mask is used to form a second interconnection layer on the left and right die areas comprising a third portion on the left die area and fourth portion different than the third portion on the right die area. The first mask is reused to form a third interconnection layer on the left and right die areas on a back side, and the second mask to form a fourth interconnection layer on the left and right die areas on a back side.

Abstract: In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate (11), and, at the same time, five isolation insulating films (12m) extending in one specific direction are formed within a monitor area (1) at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate (11), and, at the same time, five gate insulation films (13m) and five gate electrodes (14m) extending in the same direction as the isolation insulating films (12m) are formed within the monitor area (1) at the same spacing as that of the isolation insulating films (12m).

Abstract: A power semiconductor module comprising a substrate, a circuit formed thereon and having a plurality of conductor tracks that are electrically insulated from one another and power semiconductor components arranged on the conductor tracks. The latter are connected in a circuit-conforming manner by a connection device, which has an alternating layer sequence of at least two electrically conductive layers with at least one electrically insulating layer between them. In this case, the substrate has a first sealing area, which uninterruptedly encloses the circuit. Furthermore, this sealing area is connected to an assigned second sealing area on a layer of the connection device by a connection layer. According to the invention, this power semiconductor module is produced by applying pressure to the substrate, to the power semiconductor components and to the connection device.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.

Abstract: A method of manufacturing a semiconductor package includes forming a protection layer on a support plate, stacking substrates on the protection layer, electrically connecting the substrates to each other, forming a molding layer on the support plate, and removing the support plate while the protection layer remains on the substrates. The stacked substrates are offset from adjacent substrates.

Abstract: An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Abstract: Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.

Abstract: A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode 14 of the device mounting board 10 with high precision.