Other Leads Having Insulating Passage Through Base (epo) Patents (Class 257/E23.184)
  • Patent number: 11404392
    Abstract: A molded semiconductor module include: a semiconductor die attached to a main surface of a metal block. The die has a metal contact pad at a side of the die facing away from the metal block. A metal terminal has a contact region attached to the metal contact pad of the die, and a distal end region that joins the contact region and is bent upward in a direction away from the metal block such that the distal end region has a free end which terminates at a further distance from the metal block than the contact region. A molding compound encapsulates the die and covers the contact region of the metal terminal. The distal end region of the metal terminal protrudes through a surface of the molding compound that faces a same direction as the side of the die with the metal contact pad.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ivan Nikitin
  • Patent number: 9006869
    Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: JaeJoon Yoon
  • Patent number: 8692366
    Abstract: A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: April 8, 2014
    Assignee: Analog Device, Inc.
    Inventors: Xiaojie Xue, Carl Raleigh
  • Patent number: 8008761
    Abstract: An optical semiconductor apparatus composed of a cap and a base, includes: a metal package including a plurality of openings penetrating through the base from outside to inside, a lead with its end portion protruding to the inside of the base and an insulator covering a side surface of the lead being inserted into each of the openings, and the lead being insulated from the base; an insulating film with its backside bonded to the inside of the base; and a semiconductor component placed on the base or on the insulating film. The insulating film covers the opening up to the vicinity of the side surface of the lead.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: August 30, 2011
    Assignee: FiBest Limited
    Inventors: Koichi Iwaida, Michiyo Kubo
  • Patent number: 7659613
    Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Publication number: 20100013084
    Abstract: A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame.
    Type: Application
    Filed: June 16, 2009
    Publication date: January 21, 2010
    Inventor: Manuel Medeiros, III
  • Patent number: 7576423
    Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 7449726
    Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: November 11, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Nakanishi, Toshitaka Sekine, Taichi Obara
  • Publication number: 20080246140
    Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. A relay post is provided on the dielectric plate. The first band-shaped conductor is connected to the circuit pattern by an interconnection via the relay post.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 9, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 7411288
    Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, a first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed and the first and the second dielectric plate. Power supply portions are provided on a part of the sidewall, through which a first or a second band-shaped conductors is penetrating. Third dielectric plates are arranged on the base plate between the band-shaped conductors and the first dielectric plate or the second dielectric plate, having a line conductor pattern formed on their surfaces. The surfaces of the third dielectric plate are arranged at a position lower than the band-shaped conductor and higher than the surface of the first or the second dielectric plate with respect to a main surface of the base plate.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: August 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Publication number: 20080132002
    Abstract: A method of producing semiconductor packages includes the step of punching out a dam-bar and part of the region lateral to a lead of a scaling body formed by molding, the punching-out being effected by using a support block and a punch. The support block has an outer lateral surface in a region receding as much as possible from the lateral surface of the upper portion of the seal body and also has an inner lateral surface almost flush with the lateral surface of the lower portion of the seal body. The width (Wa) of the upper surface of the support block is smaller than the overhang quantity of the upper portion of the seal body. In the region lateral to the lead, the front end region (Ra) positioned immediately below the overhang section of the upper portion of the seal body has an inclined surface (Fa1) sloping inwardly downward.
    Type: Application
    Filed: May 12, 2005
    Publication date: June 5, 2008
    Inventors: Hisaho Inao, Tatsuya Hirano, Katsutoshi Shimizu