Abstract: A semiconductor packaging container allowing to use in millimeter band is provided at a low cost. The inner SIG pads and the inner GND pads, capable of a direct connection with a signal terminal of a semiconductor chip 10 are provided on the bottomed cylindrical dielectric case formed of the liquid crystal polymer. Further, the external SIG pads integrally formed with the inner SIG pads 201, 202 and the external GND pad 303 integrally formed with the inner GND pad are provided on the back of the bottom surface of the dielectric case as the external terminal. The inner GND pads and are to form the coplanar waveguide with the inner SIG pads and. Also, the inner GND pads and are to add capacitive reactance for canceling the inductance caused by the space at the semiconductor chip portion to the coplanar waveguide.

Abstract: A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members.

Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.

Abstract: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric frame. The raised shelf span defines a first thickness of the dielectric frame and a raised sidewall extending outwardly from the second side along an external perimeter of said dielectric frame defines a second thickness of said frame, with the second thickness being greater than the first thickness. Also provided is a metallic component having a flange and a pedestal that extends perpendicularly from the flange. The flange is bonded to the first side of the dielectric frame and extends across one of the pair of apertures with the pedestal extending into that aperture. A gap between the pedestal and the dielectric frame having a width of at least 0.015 inch.

Abstract: An insulated metal substrate composite has a patterned conductive layer on one surface and receives one or more electrodes of MOSFETs or other die on the patterned segments which lead to the edge of the IMS. The outer periphery of the IMS is cupped or bent to form a shallow can with two or more die fixed to and thermally coupled to the flat web of the can while electrodes on the die surfaces thermally coupled to the web of the can lead to terminals on the rim of the can which are coplanar with the bottom surfaces of the die. The electrodes can be externally or internally connected to form a half bridge circuit.

Abstract: A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame.

Abstract: Embodiments discussed herein generally include methods of fabricating MEMS devices within a structure. The MEMS device may be formed in a cavity above the structure, and additional metallization may occur above the MEMS device. The cavity may be formed by depositing an encapsulating layer over the sacrificial layers that enclose the MEMS device. The encapsulating layer may then be etched to expose portions of the sacrificial layers. The sacrificial layers are exposed because they extend through the sidewalls of the encapsulating layer. Therefore, no release holes are etched through the top of the encapsulating layer. An etchant then removes the sacrificial layers to free the MEMS device and form the cavity and an opening through the sidewall of the encapsulating layer. Another encapsulating layer may then be deposited to seal the cavity and the opening.

Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.

Abstract: A lid forms an internal space on a bottom plate together with a plurality of side walls. A dielectric plate on the bottom plate in the internal space has a smaller width than an inner surface of the lid. A projection on the inner surface of the lid has a surface area, where a distance between the projection and the bottom plate where the projection is provided is shorter than a distance between the lid and the bottom plate where the projection is not provided. The lid and the projection are coupled to pass a current therebetween. The inner surface of the lid extends further toward an inner surface of one of the side walls than does the projection. The bottom plate, the side walls, the lid, and the projection are composed of metal material. The lid and the projection are composed of the same metal material.

Abstract: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric frame. The raised shelf span defines a first thickness of the dielectric frame and a raised sidewall extending outwardly from the second side along an external perimeter of said dielectric frame defines a second thickness of said frame, with the second thickness being greater than the first thickness. Also provided is a metallic component having a flange and a pedestal that extends perpendicularly from the flange. The flange is bonded to the first side of the dielectric frame and extends across one of the pair of apertures with the pedestal extending into that aperture. A gap between the pedestal and the dielectric frame having a width of at least 0.015 inch.

Abstract: A light emitting device includes a plurality of chips efficiently disposed in a limited space of an opening that has an approximately elliptical or elongate-circular opening shape. The device includes a lead having a slit formed between a portion for bonding a wire to and a portion for mounting chips on, thereby to prevent extrusion of an adhesive and eliminate defective bonding.

Abstract: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame.

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract: An apparatus includes a housing with a plurality of restraining elements and at least one supporting element. A cover is elastically deformed by the plurality of restraining elements and the at least one supporting means. At least one substrate carrying at least one semiconductor chip is provided within the housing.

Abstract: A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.

Abstract: The power semiconductor apparatus includes a resin package made up of a power semiconductor element and a control semiconductor element which are mounted on a main front surface of a lead frame and sealed with mold resin, a power terminal led out of the resin package and electrically connected to the power semiconductor element, a control terminal led out of the resin package and electrically connected to the control semiconductor element and a cylindrical case which is formed in a manner separable from the resin package and encloses the resin package, wherein the power terminal and the control terminal are led out of lead insertion slots formed in the case, and a part of the power terminal which is led out of the case is bent along an end face of the case.

Abstract: A cerdip type of solid-state image sensing device includes a base on which photoelectric transfer devices are arranged in line along a main scanning direction, a sealed glass disposed on the base for fixing a lead frame, a wind frame disposed on the sealed glass, a transparent cover glass disposed on the wind frame, and a gripped surface for gripping the cerdip type of solid-state image sensing device.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component mounted to a substrate. The substrate carries a plurality of bond pads at a location substantially coplanar with a terminal surface of the microelectronic component. This enables a smaller package to be produced by moving the bond pads laterally inwardly toward the periphery of the microelectronic component.

Abstract: A high performance package and methods for its assembly are disclosed. A semiconductor package system of the invention is assembled in a method including the steps of affixing one or more spacers to a package substrate and affixing one or more passive components to the substrate adjacent to the spacers in order to define a plane. A semiconductor chip is affixed in the plane atop the one or more passive components and spacers and is electrically coupled to the one or more passive components.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is retractably mounted into an external housing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips (e.g., USB controller, flash memory) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. The housing includes a retractable mechanism that facilitates selective exposure of metal contacts, either by sliding a front portion of the modular USB core component into and out of a front opening of the housing, or by providing a cover plate that slidably covers the front portion of the modular USB core component.

Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.

Abstract: A method (100) of attaching a shield (52 or 82) to a substrate (40) can include the steps of circumscribing a predetermined area on the substrate with a metallized trace pattern (26), applying (101) solder to the metallized trace pattern, and optionally placing (103) components (22 and 27) on portions of the metallized trace pattern. The method can further include the steps of reflowing (104) the solder to form a selective cladded trace pattern (32 or 62) on a portion of the metallized trace pattern reserved for the shield, placing (108) the shield on the cladded trace pattern, and reflowing (109) the substrate.