Characterized By Shape Of Container Or Parts, E.g., Caps, Walls (epo) Patents (Class 257/E23.181)
  • Patent number: 10559522
    Abstract: Bottom terminated components and methods of making bottom terminated components are provided. The bottom terminated component includes a die paddle and at least one die paddle structure configured to prevent wicking into a respective thermal via of a printed circuit board. The at least one die paddle structure includes a base defining an axis, the base having an axial thickness extending from the die paddle, and a contact surface configured to contact the printed circuit board at the thermal via of the printed circuit board to prevent wicking of solder into the respective thermal via.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen M. Hugo, Mark J. Jeanson, Matthew S. Kelly
  • Patent number: 10446454
    Abstract: A semiconductor device package comprises a carrier having a through hole. A lid is over the carrier and comprises a first side wall, a second side wall, and a connection wall. The second side wall is opposite the first side wall, and the connection wall is between the first side wall and the second side wall. The lid and the carrier form a plurality of chambers. The first side wall, the second side wall and the connection wall form a space to fluidly connect the plurality of chambers.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-An Fang, Ying-Chung Chen, Cheng-Ling Huang
  • Patent number: 10042488
    Abstract: In an example, a method of processing an integrated circuit (IC) die including active circuitry formed on a substrate and a front side having a plurality of metal layers formed on the substrate. The method includes forming vias in a substrate of the IC die using a laser configured to drill the vias from the front side of the IC die. The method includes forming metal contacts on first metal pads, and metal interconnects between second metal pads and the vias, using an single electroplating process, where the first metal pads and the second metal pads are exposed parts of a top layer of the plurality of metal layers, and where the metal interconnects at least partially fill the vias. The method includes thinning the substrate of the IC die to expose the metal interconnects in the vias at a back side of the IC die opposite the front side.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 7, 2018
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Stephen L. Morein, Joseph Kurth Reynolds
  • Patent number: 9978929
    Abstract: An electronic component includes a package substrate, an electronic component element mounted on the package substrate and includes an element substrate, a support layer, and a cover member, and a mold resin layer provided on the package substrate so as to seal the electronic component element. The cover member includes a first cover member provided on the package substrate and a second cover member provided on the first cover member. The glass transition temperature of a resin material of the first cover member is higher than that of a resin material of the second cover member.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 22, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuyoshi Hira, Motoji Tsuda
  • Patent number: 9831783
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Andrew Ferencz, Shawn A Hall, Todd E Takken, Shurong Tian, Xin Zhang
  • Patent number: 9041191
    Abstract: A semiconductor package that includes a conductive can, a power semiconductor device electrically and mechanically attached to the inside surface of the can, and an IC semiconductor device copackaged with the power semiconductor device inside the can.
    Type: Grant
    Filed: November 19, 2011
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9018747
    Abstract: An optical semiconductor apparatus includes a lid body bonded to an upper surface of a frame body, the lid body having an opening at a position vertically overlapping with an optical semiconductor device. The lid body has a first portion which is positioned to surround the opening and has an upper surface to which a light-transmissive member is bonded, a second portion which is positioned to surround the first portion, and a third portion which is positioned to surround the second portion and has a lower surface to which the frame body is bonded. The upper surface of the first portion is positioned lower than an upper surface of the third portion. The second portion has a thin-walled portion positioned to surround the first portion, the thin-walled portion having a thickness thinner than that of the first portion as well as thinner than that of the third portion.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 28, 2015
    Assignee: Kyocera Corporation
    Inventor: Michikazu Nagata
  • Patent number: 8994154
    Abstract: A semiconductor proximity sensor (100) has a flat leadframe (110) with a first (110a) and a second (110b) surface, the second surface being solderable; the leadframe includes a first (111) and a second (112) pad, a plurality of leads (113, 114), and fingers (115, 118) framing the first pad, the fingers spaced from the first pad by a gap (116) which is filled with a clear molding compound. A light-emitting diode (LED) chip (120) is assembled on the first pad and encapsulated by a first volume (140) of the clear compound, the first volume outlined as a first lens (141). A sensor chip (130) is assembled on the second pad and encapsulated by a second volume (145) of the clear compound, the second volume outlined as a second lens (146). Opaque molding compound (150) fills the space between the first and second volumes of clear compound, forms shutters (151) for the first and second lenses, and forms walls rising from the frame of fingers to create an enclosed cavity for the LED.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Andy Quang Tran, Lance Wright
  • Patent number: 8963291
    Abstract: A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Noriko Miura, Kinya Goto, Masazumi Matsuura
  • Patent number: 8946877
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Patent number: 8940586
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Patent number: 8916961
    Abstract: An insulation sheet made from silicon nitride comprising: a sheet-shaped silicon-nitride substrate which contains ?-silicon-nitride crystal grains as a main phase; and a surface layer which is formed on one face or both front and back faces of surfaces of the silicon-nitride substrate and is formed from a resin or a metal which includes at least one element selected from among In, Sn, Al, Ag, Au, Cu, Ni, Pb, Pd, Sr, Ce, Fe, Nb, Ta, V and Ti. A semiconductor module structure using the insulation sheet made from silicon nitride.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: December 23, 2014
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventor: Takayuki Naba
  • Patent number: 8878357
    Abstract: An electronic component device includes a substrate, an electrode post made of a metal material, provide to stand on the substrate, and an electronic component whose connection electrode is connected to the electrode post, wherein the connection electrode of the electronic component and the electrode post are joined by an alloy layer including a metal which is different from the metal material of the electrode post.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: November 4, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Akinori Shiraishi, Mitsutoshi Higashi
  • Patent number: 8786075
    Abstract: An electrical circuit and/or lid therefor that, among other things, efficiently accommodates devices of different respective heights, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 22, 2014
    Inventors: Jeffery Alan Miks, John McCormick
  • Patent number: 8779585
    Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin M. O'Connell, Arvind K. Sinha, Kory W. Weckman, II
  • Patent number: 8754519
    Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Patent number: 8736044
    Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: May 27, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mudasir Ahmad, Kuo-Chuan Liu, Mohan Nagar, Bangalore Shanker
  • Patent number: 8729697
    Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies AG
    Inventors: Horst Theuss, Klaus Elian
  • Patent number: 8692366
    Abstract: A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: April 8, 2014
    Assignee: Analog Device, Inc.
    Inventors: Xiaojie Xue, Carl Raleigh
  • Patent number: 8643169
    Abstract: A packaged semiconductor device with a cavity formed by a cover or lid mounted to a substrate. The lid covers one or more semiconductor sensor dies mounted on the substrate. The dies are coated with a gel or spray on coating, and the lid is encapsulated with a mold compound. A hole or passage may be formed through the cover and mold compound to expose the sensor dies to selected environmental conditions.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: February 4, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kai Yun Yow, Poh Leng Eu
  • Patent number: 8637978
    Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: January 28, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath
  • Patent number: 8624383
    Abstract: The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device; a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: January 7, 2014
    Inventors: Yu-Lin Yen, Chen-Mei Fan
  • Publication number: 20130320517
    Abstract: A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Dwayne Richard Shirley
  • Patent number: 8587114
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Suresh D. Kadakia, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Patent number: 8575740
    Abstract: An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuyuki Arai, Yuko Tachimura, Yohei Kanno, Mai Akiba
  • Publication number: 20130285228
    Abstract: A bonded semiconductor device comprising a support substrate, a semiconductor device located with respect to one side of the support substrate, a cap substrate overlying the support substrate and the device, a glass frit bond ring between the support substrate and the cap substrate, an electrically conductive ring between the support substrate and the cap substrate. The electrically conductive ring forms an inner ring around the semiconductor device and the glass frit bond ring forms an outer bond ring around the semiconductor device.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Inventors: Ruben B. Montez, Robert F. Steimle
  • Patent number: 8558371
    Abstract: Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JiSun Hong, Taeje Cho, Un-Byoung Kang, Hyuekjae Lee, Youngbok Kim, Hyung-sun Jang
  • Patent number: 8513043
    Abstract: The present invention generally relates to methods for producing MEMS or NEMS devices and the devices themselves. A thin layer of a material having a lower recombination coefficient as compared to the cantilever structure may be deposited over the cantilever structure, the RF electrode and the pull-off electrode. The thin layer permits the etching gas introduced to the cavity to decrease the overall etchant recombination rate within the cavity and thus, increase the etching rate of the sacrificial material within the cavity. The etchant itself may be introduced through an opening in the encapsulating layer that is linearly aligned with the anchor portion of the cantilever structure so that the topmost layer of sacrificial material is etched first. Thereafter, sealing material may seal the cavity and extend into the cavity all the way to the anchor portion to provide additional strength to the anchor portion.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 20, 2013
    Assignee: Cavendish Kinetics Inc.
    Inventors: Mickael Renault, Joseph Damian Gordon Lacey, Vikram Joshi, Thomas L. Maguire
  • Patent number: 8497577
    Abstract: An apparatus includes a Micro Electrical Mechanical System (MEMS) having electrical contacts and a MEMS device in electrical communication with the electrical contacts. A lid is oriented over the MEMS device and not the electrical contacts. The lid has a base region and a top region, the base region being wider in dimension than the top region and oriented in closer proximity to the MEMS device than the top region.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: July 30, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, David M. Craig, Charles C. Haluzak
  • Publication number: 20130127036
    Abstract: The present disclosure relates to a bump processing method and/or resulting MEMS-CMOS structure, in which one or more anti-stiction bumps are formed within a substrate prior to the formation of a cavity in which the one or more anti-stiction bumps reside. By forming the one or more anti-stiction bumps prior to a cavity, the sidewall angle and the top critical dimension (i.e., surface area) of the one or more anti-stiction bumps are reduced. The reduction in sidewall angle and critical dimension reduces stiction between a substrate and a moveable part of a MEMS device. By reducing the size of the anti-stiction bumps through a processing sequence change, lithographic problems such as reduction of the lithographic processing window and bump photoresist collapse are avoided.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chris Kuo, Lee-Chuan Tseng
  • Publication number: 20130119529
    Abstract: A semiconductor device includes a substrate, a first die attached to the substrate, and a lid coupled to the substrate. The lid defines a cavity for engaging the first die, and the lid has a die enclosure barrier having ends extending downwardly into the cavity. The ends of the die enclosure barrier are attached to the substrate and a thermal interface material is disposed between the first die and the lid, thermally connecting the first die to the lid.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Yi LIN, Po-Yao LIN
  • Publication number: 20130113054
    Abstract: A packaged semiconductor device with a cavity formed by a cover or lid mounted to a substrate. The lid covers one or more semiconductor sensor dies mounted on the substrate. The dies are coated with a gel or spray on coating, and the lid is encapsulated with a mold compound. A hole or passage may be formed through the cover and mold compound to expose the sensor dies to selected environmental conditions.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Kai Yun Yow, Poh Leng Eu
  • Publication number: 20130083038
    Abstract: This disclosure provides systems, methods and apparatus for fabricating spacers for electromechanical systems devices. In one aspect, a method of forming a spacer on a spacer portion of a device surface of an electromechanical systems device includes exposing the device surface to spacer particles suspended in a fluid. The spacer particles are allowed to attach to the spacer portion. Each of the spacer particles can have at least one dimension of about 1 micron to 10 microns. The electromechanical systems device can also include a sacrificial layer that is subsequently removed between the device surface and a substrate surface of a substrate on which the electromechanical systems device is formed.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventor: Rihui HE
  • Publication number: 20130075888
    Abstract: A semiconductor package is provided, which includes: a micro electro mechanical system (MEMS) chip; a cap provided on the MEMS chip; an electronic element provided on the cap including a plurality of first conductive pads and second conductive pads; a plurality of first conductive elements electrically connected to the first conductive pads and the MEMS chip; a plurality of second conductive elements formed on the second conductive pads, respectively; and an encapsulant formed on the MEMS chip covering the cap, the electronic element, the first conductive elements and the second conductive elements, with the second conductive elements being exposed from the encapsulant. Thus, the size of the semiconductor package is reduced. A method of fabricating the semiconductor package is also disclosed.
    Type: Application
    Filed: July 5, 2012
    Publication date: March 28, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hong-Da Chang, Hsin-Yi Liao
  • Patent number: 8395253
    Abstract: A semiconductor package which includes a substrate formed from AlN and electrical terminals formed from tungsten on at least one surface of the substrate by bulk metallization to serve as electrical connection to a component within the package.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: March 12, 2013
    Assignee: International Rectifier Corporation
    Inventor: Weidong Zhuang
  • Publication number: 20130056863
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a stiffener, having a stiffener opening completely through the stiffener, on the substrate; molding an encapsulation on the substrate and directly on an outer upper periphery surface of the stiffener and exposing an inner upper periphery surface of the stiffener, the encapsulation exposing a portion of the substrate; mounting an integrated circuit over the substrate and within the perimeter of the stiffener; and attaching a lid plate on the inner upper periphery surface of the stiffener and over the integrated circuit, the lid plate extending above an encapsulation top side.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 7, 2013
    Inventors: HeeJo Chi, NamJu Cho, HanGil Shin
  • Publication number: 20130049184
    Abstract: An electronic device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, a sealing member 16 provided on the support substrate 12 to surround the sealing region, a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween, and a spacer 23 arranged between the support substrate 12 and the sealing substrate 17. The electric circuit 14 includes an electronic element 24 having an organic layer. The sealing member 16 and the spacer 23 are formed using the same material.
    Type: Application
    Filed: March 4, 2011
    Publication date: February 28, 2013
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Kenji Kasahara, Masaya Shimizu, Tomoki Kurata
  • Publication number: 20130032935
    Abstract: A method and structures are provided for implementing enhanced thermal conductivity between a lid and heat sink for stacked modules. A chip lid and lateral heat distributor includes cooperating features for implementing enhanced thermal conductivity. The chip lid includes a groove along an inner side wall including a flat wall surface and a curved edge surface. The lateral heat distributor includes a mating edge portion received within the groove. The mating edge portion includes a bent arm for engaging the curved edge surface groove and a flat portion. The lateral heat distributor is assembled into place with the chip lid, the mating edge portion of the lateral heat distributor bends and snaps into the groove of the chip lid. The bent arm portion presses on the curved surface of the groove, and provides an upward force to push the flat portion against the flat wall surface of the groove.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin M. O'Connell, Arvind K. Sinha, Kory W. Weckman
  • Patent number: 8358003
    Abstract: A surface mount electronic device packaging assembly includes a body having an aperture defined therethrough. The aperture is adapted to receive an electronic device therein. The body has a first surface and a second surface. An electrically conductive contact pad is disposed on the first surface of the body. The contact pad is adapted to receive a lead from the electronic device. A thermally conductive base pad is disposed on the second surface of the body. A top surface of the base pad is adapted to receive the electronic device thereon.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: January 22, 2013
    Assignee: Electro Ceramic Industries
    Inventor: Herbert W. Schlomann
  • Patent number: 8344489
    Abstract: A semiconductor device of the invention includes: a substrate having a hollowed hollow section on a top surface; a semiconductor chip mounted in the hollow section of the substrate; and a lid having a substantially plate-shaped top plate section that opposes the substrate and covers the hollow section, and having at least one pair of side wall sections that project from a circumference of the top plate section towards the substrate and that engage with a side surface of the substrate. The substrate and the lid can be accurately positioned.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 1, 2013
    Assignee: Yamaha Corporation
    Inventors: Hiroshi Saitoh, Toshihisa Suzuki, Shingo Sakakibara
  • Patent number: 8324728
    Abstract: A semiconductor packaged device, and method of packaging that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: December 4, 2012
    Assignee: Skyworks Solutions, Inc.
    Inventor: Behnam Tabrizi
  • Patent number: 8314485
    Abstract: An electronic component has a board, a semiconductor element mounted on an upper surface of the board, a ground electrode formed in a region surrounding the semiconductor element on the upper surface of the board, a conductive cap that overlaps the board such that the semiconductor element is covered therewith, and a conductive joining member that joins a whole periphery of a lower surface of the conductive cap to the ground electrode. The conductive cap includes a pressing portion on the lower surface thereof The lower surface of the conductive cap and the ground electrode are joined by the conductive joining member on an outer peripheral side of the pressing portion.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: November 20, 2012
    Assignee: OMRON Corporation
    Inventors: Kazuyuki Ono, Yoshio Tanaka, Kiyoshi Nakajima, Naoto Kuratani, Tomofumi Maekawa
  • Patent number: 8309388
    Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Kurt P. Wachtler, Wei-Yan Shih, Gregory E. Howard
  • Publication number: 20120267773
    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.
    Type: Application
    Filed: November 19, 2009
    Publication date: October 25, 2012
    Applicant: SILEX Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Tomas Bauer
  • Patent number: 8288791
    Abstract: A package body (1) with an upper side (2), with an underside (22), opposite from the upper side (2), and with a side surface, which connects the upper side (2) and the underside (22) and is provided as a mounting surface (19), the package body (1) having a plurality of layers (8) which contain a ceramic material, and a main direction of extent of the layers (23, 24, 25) extending transversely in relation to the mounting surface (19). Furthermore, a method for producing a package body (1) is provided.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: October 16, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Georg Bogner, Karlheinz Arndt
  • Publication number: 20120256308
    Abstract: A method for sealing a cavity is disclosed. The method includes depositing a membrane layer on top of a sacrificial layer, etching release holes into the membrane layer, and removing at least a portion of the sacrificial layer through the release holes to form a cavity. Prior to removing the sacrificial layer portion, the method includes producing a narrowing layer on the side walls of the release holes. The narrowing layer can be a sealing layer that seals off the release holes after a reflow step. Alternatively, the narrowing layer can be a layer that does not have a sealing function and is used to narrow the holes, allowing the holes to be sealed without a sealing or other material entering the cavity. The narrowing layer may be deposited by conformal deposition followed by an anisotropic etch or by direct deposition on the side walls of the release holes.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 11, 2012
    Applicant: IMEC
    Inventor: Philippe Helin
  • Publication number: 20120248553
    Abstract: A sensor device and a manufacturing method thereof are provided in which no resin seal is used when a sensor is packaged, a change in connection relation according to a change in specifications of the control IC and others is facilitated when a control IC is packaged together with the sensor and high reliability is kept. The sensor device of the present invention includes a substrate containing an organic material and being formed a wiring, a sensor arranged on the substrate and electrically connected to the wiring, and a package cap arranged on the substrate and containing an organic material and covering the sensor, and the inside of the package cap is hollow.
    Type: Application
    Filed: May 18, 2012
    Publication date: October 4, 2012
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventor: Takamasa TAKANO
  • Patent number: 8269320
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rui Huang, Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan
  • Publication number: 20120228756
    Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 13, 2012
    Inventors: Tobias KOLLETH, Pascal Stumpf, Christian Joos
  • Patent number: 8247889
    Abstract: The present invention relates to a package having an inner shield and a method for making the same. The package includes a substrate, a plurality of electrical elements, a molding compound, an inner shield and a conformal shield. The electrical elements are disposed on the substrate. The molding compound is disposed on a surface of the substrate, encapsulates the electrical elements, and includes at least one groove. The groove penetrates a top surface and a bottom surface of the molding compound and is disposed between the electrical elements, and there is a gap between a short side of the groove and a side surface of the molding compound. The inner shield is disposed in the groove and electrically connected to the substrate. The conformal shield covers the molding compound and a side surface of the substrate, and electrically connects the substrate and the inner shield.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: August 21, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuo-Hsien Liao, Jian-Cheng Chen