Abstract: A semiconductor device or power electronic device is described. The device includes a pair of pole pieces, each having a profiled surface. A semiconductor body or wafer, preferably of wide bandgap electronic material, is located between the pole pieces and includes contact metallization regions. The semiconductor body produces an electric field that emerges from an edge region. Passivation means includes a first or radially inner part in contact with the edge region of the semiconductor body and which diffuses the electric field as it emerges from the edge region and a second or radially outer part. The second part of the passivation is in contact with the first part and provides a substantially void-free interface with the profiled surface of each pole piece. The device may be immersed in a dielectric liquid.

Abstract: A light emitting device package is provided comprising a light emitting device including at least one light emitting diode and a body including a first lead frame on which the light emitting device is mounted and a second lead frame spaced apart from the first lead frame, wherein at least one of the first and second lead frames is extending to a bending region in a first direction by a predetermined length on the basis of an outer surface of the body and is bent in a second direction intersecting the first direction.

Abstract: The respective main electrodes of the semiconductor switching elements such as IGBTs, which are respectively mounted on the plurality of insulating boards, are electrically connected to each other via the conductor member. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacity and the parasitic inductance of each semiconductor switching element.

Abstract: An over-voltage protection thyristor has reduced junction capacitance making it suitable for use in high bandwidth applications. The reduced capacitance is achieved through the introduction of a deep base region. The deep base region has a graded doping concentration which reduces with depth into the substrate. The thyristor is useful for protecting sensitive electrical equipment from transient surges.

Abstract: A method for making semiconductor chips having coated portions can include mounting the chips in lead frames, stacking the lead frames in an orientation in which a portion of one lead frame masks a portion of a chip mounted on another lead frame but leaves another portion of the chip mounted on the other lead frame exposed to receive a coating, and depositing a coating on the stacked lead frames using, for example, an evaporative coating machine. In this manner, the coating is deposited on exposed portions of chips, such as its edges, and is not deposited on masked portions of chips, such as bond pads.

Abstract: A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.

Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).

Abstract: A semiconductor chip 36 is mounted on a package substrate 30 with its circuit side facing to a board 38. Heat is dissipated from an upper side of the semiconductor chip 36 opposite to the circuit side. A sealing resin 32 seals around the periphery of the semiconductor chip 36 so that the upper side of the semiconductor chip 36 is exposed to atmosphere. A fixing member 34 is buried in the sealing resin 32 so that a hook 40 formed on the tip of the fixing member 34 extends above the upper side of the semiconductor chip 36. A spreader 10 dissipates heat emitted from the semiconductor chip 36. A guiding slot 12 is formed on the side facing to the package substrate 30 of the spreader 10. The hooks 40 of the fixing members 34 are inserted into the guiding slots 12 respectively, and then the spreader 10 is rotated by predetermined angle against the package substrate 30. Then, the hooks 40 travel along the slots 12.

Abstract: A package for a die comprising a thermally conducting carrier; a dielectric frame on the carrier, the frame having a recess therein for receiving a die; an electrically insulating lid adapted to be positioned on the frame to cover the recess, the lid having dimensions such that when covering the recess a portion of the lid extends beyond the frame creating at least one overhang; the frame having at least one electrically conducting frame path; and the lid having a corresponding electrically conducting lid path arranged such that when the lid is positioned on the frame a portion of the lid path overlies the frame path, the lid path extending onto the overhang beyond the frame.

Abstract: The invention relates to a power semiconductor module having at least one semiconductor chip (11) made of a semiconductor material and having a first and a second main electrode (12, 13), a first and a second main connection (91, 92) and a contact lamina (2) in electrical contact with the first main electrode (12) and the first main connection (92). The contact lamina (2) contains an alloying partner which can form a eutectic with the semiconductor material. According to the invention, the contact lamina is coated with an electrically conductive protective layer (31, 32) that prevents formation of a fixed material connection between the first main electrode (12) and the contact lamina (2).

Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.

Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.