Abstract: In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The integrated circuit further includes an auxiliary transistor with an auxiliary control terminal, a first auxiliary load terminal and a second auxiliary load terminal. The first auxiliary load terminal is electrically coupled to the power control terminal. The integrated circuit further includes a capacitor with a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer. The capacitor dielectric layer includes at least one of a ferroelectric material and a paraelectric material. The first capacitor electrode is electrically coupled to the auxiliary control terminal.

Abstract: A non-linear kerf monitor, methods of manufacture and design structures are provided. The structure includes a coplanar waveguide provided in a kerf of a wafer between a first chip and a second chip. The structure further includes a shunt switch and a series switch coupled to the coplanar waveguide.

Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.

Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.

Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.

Abstract: A charge pump circuit includes MOSFETs and MOS capacitors formed on the same substrate. Each of the MOS capacitors has a multiplicity of first electrodes formed in one region of the substrate, insulating layers formed on/above respective substrate regions between neighboring first electrodes, each layer covering at least the respective substrate region, and a multiplicity of second electrodes formed on/above the respective insulating layers. The MOS capacitors have improved frequency response.

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor device may include a semiconductor element disposed on a substrate and including an insulating layer and a gate electrode, a doped region having a first conductivity-type on the substrate, a conductive interconnection electrically connected to the gate electrode, and a first contact plug having a second conductivity-type and electrically connecting the conductive interconnection and the doped region to each other and constituting a Zeiler diode by junction with the doped region.

Abstract: A semiconductor device with first and second groups of transistors, the second group transistors each having a lower operating voltage than that of each of said transistors in said first group, the first group transistors have first gate electrodes formed from a silicon based material layer on a semiconductor substrate through a first gate insulating film, the second group transistors have second gate electrodes formed such that metal based gate materials are respectively filled in gate formation trenches formed in an interlayer insulating film on the semiconductor substrate through a second gate insulating film, and a resistor on the substrate has a resistor main body utilizing the silicon based material layer and is formed on the substrate through an insulating film.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

Abstract: A semiconductor memory device includes at least one supporting pattern on a substrate, a storage node penetrating the supporting pattern, an electrode layer disposed around the storage node and the supporting pattern, and a capacitor dielectric interposed between the storage node and the electrode layer. The supporting pattern includes germanium oxide.

Abstract: A two-layer electrode structure is provided. A protection diode is provided not to overlap a gate pad portion. Cells and a first one of source electrode layers can be provided below the gate pad portion, so that the differences in resistance among various points in the source electrode layers can be decreased. In addition, the protection diode is positioned adjacent to a device region and at an end portion, of a chip, outward of the device region in such a way as to be in the closest proximity to the gate pad portion. A larger device region with efficient transistor operation can thus be secured, and the resistance of the first source electrode layer below a wiring portion can be reduced.

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract: To constitute a display panel only by transistors having the same conductivity type is difficult if a p-type transistor is adopted as a driving transistor. By constituting a circuit formed in the display panel by transistors having the same conductivity type, manufacturing process can be reduced, and cost reduction can be achieved. In the invention, an n-type transistor is used as a driving transistor for driving a light emitting element, and the driving transistor and the light emitting element constitute a source follower circuit.

Abstract: An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate.

Abstract: A semiconductor device that is less influenced by variations in characteristics between transistors or variations in a load, and is efficient even for normally-on transistors is provided. The semiconductor device includes at least a transistor, two wirings, three switches, and two capacitors. A first switch controls conduction between a first wiring and each of a first electrode of a first capacitor and a first electrode of a second capacitor. A second electrode of the first capacitor is connected to a gate of the transistor. A second switch controls conduction between the gate and a second wiring. A second electrode of the second capacitor is connected to one of a source and a drain of the transistor. A third switch controls conduction between the one of the source and the drain and each of the first electrode of the first capacitor and the first electrode of the second capacitor.

Abstract: A DRAM memory structure at least includes a strip semiconductive material disposed on a substrate and extending along a first direction, a split gate disposed on the substrate and extending along a second direction, a dielectric layer at least sandwiched between the split gate and the substrate, a gate dielectric layer at least sandwiched between the split gate and the strip semiconductive material, and a capacitor unit. The split gate independently includes a first block and a second block to divide the strip semiconductive material into a source terminal, a drain terminal and a channel. The capacitor unit is electrically connected to the source terminal.

Abstract: Type-switching transistors, electronic devices including the same, and methods of operating thereof are provided. A type-switching transistor may include a plurality of gates corresponding to a channel layer. The plurality of gates may include a first gate for switching a type of the transistor and a second gate for controlling ON/OFF characteristics of the channel layer. The first and second gates may be disposed on one side of the channel layer so that the channel layer is not disposed between the first and second gates.

Abstract: A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

Abstract: Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.

Abstract: A Schottky diode includes a semiconductor layer formed on a semiconductor substrate; first and second trenches formed in the semiconductor layer where the first and second trenches are lined with a thin dielectric layer and being filled partially with a trench conductor layer and remaining portions of the first and second trenches are filled with a first dielectric layer; and a Schottky metal layer formed on a top surface of the semiconductor layer between the first trench and the second trench. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in each of the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate.

Abstract: A semiconductor device comprises: a MOS transistor connected between a power supply terminal and a ground terminal; a first diode connected between a drain and a gate of the MOS transistor; a second diode connected between the drain and the gate of the MOS transistor, in series with the first diode, and having a forward direction which is opposite to that of the first diode; and a capacitor connected between the drain and the gate of the MOS transistor, in series with the first diode and the second diode.

Abstract: Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided.

Abstract: A semiconductor device includes a semiconductor layer stack formed on a substrate, a first ohmic electrode and a second ohmic electrode which are formed on the semiconductor layer stack, and are spaced from each other, a first control layer formed between the first ohmic electrode and the second ohmic electrode, and a first gate electrode formed on the first control layer. The first control layer includes a lower layer, an intermediate layer which is formed on the lower layer, and has lower impurity concentration than the lower layer, and an upper layer which is formed on the intermediate layer, and has higher impurity concentration than the intermediate layer.

Abstract: A semiconductor device has a transistor in which a resistance is inserted between a gate electrode and a source electrode, and a diode inserted between the gate electrode and the source electrode in series in relation to the resistance.

Abstract: In one embodiment, a circuit, which comprises a resistor and a pMOS or cMOS transistor, has the characteristic of an inductor and produces an inductive impedance that operates over a substantially full range of a direct-current bias.

Abstract: A semiconductor structure including a high-voltage transistor; voltage dropping circuitry, at least part of which is overlapping the high-voltage transistor; at least one intermediate contact point to the voltage dropping circuitry, connected to at least one intermediate position between a first and a second end of the voltage dropping circuitry; and at least one external connection connecting the at least one intermediate contact point to outside of the semiconductor structure.

Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.

Abstract: A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

Abstract: A semiconductor device includes a gate electrode on a gate insulating film over a semiconductor substrate, a first sidewall insulating film on a side surface of the gate electrode, and source and drain regions, each including a pocket diffusion layer of a first conductivity type, and first and second diffusion layers of a second conductivity type. The pocket diffusion layer is disposed in the semiconductor substrate. The first diffusion layer of a second conductivity type extends over the pocket diffusion layer. The first diffusion layer faces toward the gate electrode through the first sidewall insulating film. The second diffusion layer over the first diffusion layer is higher in impurity concentration than the first diffusion layer. The second diffusion layer is separated by the first diffusion layer from the pocket diffusion layer, and has a side surface which faces toward the first sidewall insulating film through the first diffusion layer.

Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Abstract: A capacitor structure applied to an integrated circuit (IC) is provided. The capacitor structure includes a metal-oxide semiconductor (MOS) capacitor and two metal structures with different structures. The MOS capacitor has a first terminal and a second terminal. The two metal capacitors are formed above the MOS capacitor and respectively coupled between the first terminal and the second terminal. Subject to the confined chip area, the capacitance of the above-mentioned capacitor structure can still reach the design value, and the above-mentioned capacitor structure is further characterized by a large amount of current flow.

Abstract: The present invention discloses a power device with integrated power transistor and Schottky diode and a method for making the same. The power device comprises a power transistor having a drain region, a Schottky diode in the drain region of the power transistor, and a trench-barrier near the Schottky diode. The trench-barrier is provided to reduce a reverse leakage current of the Schottky diode and minimizes the possibility of introducing undesired parasitic bipolar junction transistor in the power device.

Abstract: A device comprises a substrate having at least one active region, an insulating layer above the substrate, and an electrode in a gate electrode layer above the insulating layer, forming a metal-oxide-semiconductor (MOS) capacitor. A first contact layer is provided on the electrode, having an elongated first pattern extending in a first direction parallel to the electrode. A contact structure contacts the substrate. The contact structure has an elongated second pattern extending parallel to the first pattern. A dielectric material is provided between the first and second patterns, so that the first and second patterns and dielectric material form a side-wall capacitor connected in parallel to the MOS capacitor.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Abstract: Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

Abstract: Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 K?˜30 K?) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

Abstract: A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

Abstract: Provided is a semiconductor device capable of preventing destruction of an electrode having a pillar shape and densely arranged. The semiconductor device having a field-effect transistor and a capacitor having a pillar shape, the semiconductor device includes: a first electrode having a pillar shape and electrically connected to an impurity diffusion region of the field-effect transistor; a dielectric film formed at least on a side of the first electrode; a second electrode formed on the dielectric film; and a support film extending in a direction crossing a length direction of the first electrode having the pillar shape, and formed by a boron-added silicon nitride film connected to the first electrode by penetrating through at least a part of the second electrode.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a substrate that includes a doped well disposed therein. The doped well and the substrate have opposite doping polarities. The high voltage semiconductor device includes an insulating device disposed over the doped well. The high voltage semiconductor device includes an elongate resistor disposed over the insulating device. A non-distal portion of the resistor is coupled to the doped well. The high voltage semiconductor device includes a high-voltage junction termination (HVJT) device disposed adjacent to the resistor.

Abstract: The invention relates to a signal line driving circuit having a first and a second current source circuits, a shift register, and a constant current source for video signal, in which the first current source circuit is disposed in a first latch and the second current source circuit is disposed in a second latch. The first current source circuit includes capacitive means for converting the current supplied from the constant current source for video signal into a voltage, according to a sampling pulse supplied from the shift register, and supplying means for supplying the current corresponding to the converted voltage.

Abstract: In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer.

Abstract: An integrated circuit ESD protection circuit (270) is formed with a combination device consisting of a gated diode (271) and an output buffer MOSFET (272) where the body tie fingers of a first conductivity type (307) are formed in the substrate (301, 302) and isolated from the drain regions of a second conductivity type (310) using a plurality of diode poly fingers (231, 232) which are interleaved with a plurality of poly gate fingers (204, 205) forming the output buffer MOSFET (272).

Abstract: A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 ?m or more.

Abstract: In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. The present invention is a semiconductor integrated circuit device formed over a semi-insulating compound semiconductor substrate in which a first electrode of an MIM capacitor electrically coupled to an external pad is electrically coupled to the semi-insulating compound semiconductor substrate, and on the other side, a second electrode of the MIM capacitor is electrically coupled to the semi-insulating compound semiconductor substrate.

Abstract: In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.

Abstract: A semiconductor device includes a substrate with one or more active regions and an isolation layer formed to surround an active region and to extend deeper into the substrate than the one or more active regions. The semiconductor further includes a gate electrode, which covers a portion of the active region, and which has one end; portion thereof extending over the isolation layer.