Abstract: An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.

Abstract: A semiconductor device and a power converter using it wherein a switching power device and a flywheel diode are connected in series, the flywheel diode includes a region having a Schottky junction to operate as a Schottky diode and a region having a pn junction to operate as a pn diode and control operation is performed such that when current flows forwardly through the flywheel diode, the pn diode operates and when the flywheel diode recovers backwardly, the Schottky diode operates mainly.

Abstract: A semiconductor device includes an IGBT, a constant voltage circuit, and protection Zener diodes. The IGBT makes/breaks a low-voltage current flowing in a primary coil. The constant voltage circuit and the protection Zener diodes are provided between an external gate terminal and an external collector terminal. The constant voltage circuit supplies a constant gate voltage to the IGBT to thereby set a saturation current value of the IGBT to a predetermined limiting current value. The IGBT has the saturation current value in a limiting current value range of the semiconductor device.

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.

Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Abstract: Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor.

Abstract: Mutual triggering of electrostatic discharge (ESD) fingers is improved by creating a base contact in each individual finger and connecting all of these base contacts in parallel. The local base contact in each ESD finger is located at a position where the base voltage significantly increases when the ESD current increases. Thus when an ESD finger is triggered its local base voltage will tend to significantly increase. Since all of the ESD finger bases are connected in parallel this local voltage increase will forward bias the base-emitter junctions of the other ESD fingers, thus triggering them all. By sharing the triggering current from the fastest ESD finger with the slower ones ensures that all ESD fingers are triggered during an ESD event.

Abstract: A metal gate electrode and a poly-silicon resistance element are mixedly mounted in the same semiconductor substrate. The metal gate electrode is formed on a first gate insulating film and includes a first gate metal film and a first gate silicon film. The poly-silicon resistance element includes a silicon film pattern formed on a laminated pattern which includes a first laminate insulating film, a first laminate metal film, and a second laminate insulating film. The first laminate insulating film and the first gate insulating film are formed from a common insulating film; the first laminate metal film and the first gate metal film are formed from a common metal film, and the silicon firm pattern and the first gate silicon film are formed from a common silicon film. In a planar view, a footprint of the silicon film pattern is included within the second laminate insulating film.

Abstract: The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

Abstract: A semiconductor device includes a semiconductor substrate having a first gate groove having first and second sides opposite to each other; a first diffusion region underneath the first gate groove; a second diffusion region in the semiconductor substrate, the second diffusion region covering an upper portion of the first side of the first gate groove; and a third diffusion region in the semiconductor substrate. The third diffusion region covers the second side of the first gate groove. The third diffusion region is coupled to the first diffusion region. The third diffusion region has a bottom which is deeper than a bottom of the first gate groove. The bottom of the third diffusion region is different in level from the bottom of the first diffusion region.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT element including a collector region; a FWD element including a cathode region adjacent to the collector region; a base layer on the substrate; multiple trench gate structures including a gate electrode. The base layer is divided by the trench gate structures into multiple first and second regions. Each first region includes an emitter region contacting the gate electrode. Each first region together with the emitter region is electrically coupled with an emitter electrode. The first regions include collector side and cathode side first regions, and the second regions include collector side and cathode side second regions. At least a part of the cathode side second region is electrically coupled with the emitter electrode, and at least a part of the collector side second region has a floating potential.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.

Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A semiconductor device includes an output port that has a first lateral double diffused metal oxide semiconductor (LDMOS) device and an electrostatic discharge protection device that has a second LDMOS device and a bipolar transistor and that protects the output port from electrostatic discharge. A breakdown voltage of the second LDMOS device is equal to or lower than a breakdown voltage of the first LDMOS device.

Abstract: The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.

Abstract: An IGBT module is provided. The IGBT module has at least a first individual IGBT with a first softness during switching-off the IGBT module, and at least a second individual IGBT connected in parallel to the at least one first IGBT. The at least one second individual IGBT has a second softness during switching-off the IGBT module which is different than the first softness. Further a circuit and an electronic power device having two individual IGBTs, which are connected in parallel, are provided.

Abstract: A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.

Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

Abstract: Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET.

Abstract: A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Abstract: The invention is directed to a protection circuit for protecting IC chips against ESD. An ESD protection circuit for an integrated circuit chip may comprise an isolated NMOS transistor, which may comprise an isolation region isolating a backgate from a substrate, and a first and second doped regions and a gate formed on the backgate. The ESD protection circuit may further comprise a first terminal to connect the isolation region to a first electrical node, and a second terminal to connect the second doped region to a second electrical node. The first electrical node may have a higher voltage level than the second electrical node, and the gate and backgate may be coupled to the second terminal.

Abstract: The present invention provides a smoke-free ESD protection structure used in integrated circuit devices. A JFET or n-channel MOS transistor is coupled between an I/O pad, and a transistor and diode, wherein the JFET or n-channel MOS transistor limits the current flowing through the diode and transistor to prevent the integrated circuit device from heating up and catching on fire or smoke during the smoke test. Moreover, the integrated circuit device will not be damaged by the smoke test.

Abstract: In an NLDMOS array, the source fingers are terminated by p+ Pbody diffusions or Pbody diffusions. The drain-source spacing is reduced by arranging p+ Pbody regions for contacting the Pbody, in line with n+ source regions to define source fingers with interdigitated p+ Pbody regions.

Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.

Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Abstract: A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device and a power converter using it wherein a switching power device and a flywheel diode are connected in series, the flywheel diode includes a region having a Schottky junction to operate as a Schottky diode and a region having a pn junction to operate as a pn diode and control operation is performed such that when current flows forwardly through the flywheel diode, the pn diode operates and when the flywheel diode recovers backwardly, the Schottky diode operates mainly.

Abstract: A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent.

Abstract: A MOS-gate power semiconductor device is provided which includes: one or more P-type wells formed under one or more of a gate metal electrode and a gate bus line and electrically connected to an emitter metal electrode; and one or more N-type wells formed in the P-type well and electrically connected to one or more of the gate metal electrode and the gate bus line. According to this configuration, it is possible to suppress deterioration and/or destruction of a device due to an overcurrent.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device.

Abstract: A reverse-conducting semiconductor device (RC-IGBT) including a freewheeling diode and an insulated gate bipolar transistor (IGBT), and a method for making the RC-IGBT are provided. A wafer has first and second sides emitter and collector sides of the IGBT, respectively. At least one layer of a first or second conductivity type is created on the second side before at least one layer of a different conductivity type is created on the second side. The at least one layer of the first or second conductivity type and the at least one layer of the different conductivity type are arranged alternately in the finalized RC-IGBT. A second electrical contact, which is in direct electrical contact with the layers of the first or second and different conductivity types, is created on the second side. A shadow mask is applied on the second side, and the layer of the first or second conductivity type is created through the shadow mask.

Abstract: A capacitor structure in trench structures of a semiconductor device includes conductive regions made of metallic and/or semiconducting materials. The conducting regions are surrounded by a dielectric and form stacked layers in the trench structure of the semiconductor device.

Abstract: The size of a light emitting device is reduced. The light emitting device for flash photography includes: a luminescent xenon tube; IGBT for the discharge switch of the xenon tube; a capacitor for discharging the xenon tube; and MOSFET for the charge switch of the capacitor. A semiconductor device used in this light emitting device is obtained by sealing the following in a package: a semiconductor chip in which the IGBT is formed; a semiconductor chip in which the MOSFET is formed; a semiconductor chip in which a drive circuit of the IGBT and a control circuit of the MOSFET are formed; and multiple leads coupled thereto.

Abstract: This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal.

Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

Abstract: A component arrangement including a MOS transistor having a field electrode is disclosed. One embodiment includes a gate electrode, a drift zone and a field electrode, arranged adjacent to the drift zone and dielectrically insulated from the drift zone by a dielectric layer a charging circuit, having a rectifier element connected between the gate electrode and the field electrode.

Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Abstract: A planar combined structure of a bipolar junction transistor (BJT) and n-type/p-type metal semiconductor field-effect transistors (MESFETs) and a method for forming the structure. The n-type GaN MESFET is formed at the same time when an inversion region (an emitter region) of the GaN BJT is formed by an ion implantation or impurity diffusion method by using a particular mask design, while a p-type GaN region is at the same time is formed as the p-type GaN MESFET. Namely, the n-type channel of the n-type MESFET is formed by the ion implantation or impurity diffusion method when the BJT is formed with the same ion implantation or impurity diffusion method performed, while a region of the p-type GaN without being subject to the ion implantation or impurity diffusion method is formed as the p-type MESFET. As such, the BJT is formed currently with the n-type/p-type MESFETs on the same GaN crystal growth layer as a planar structure.

Abstract: An integrated circuit includes a high voltage NPN bipolar transistor and a low voltage device. The NPN bipolar transistor includes a lightly doped p-well as the base region of the transistor while the low voltage devices are built using standard, more heavily doped p-wells. By using a process including a lightly doped p-well and a standard p-well, high and low voltage devices can be integrated onto the same integrated circuit. In one embodiment, the lightly doped p-well and the standard p-well are formed by performing ion implantation using a first dose to form the lightly doped p-well, masking the lightly doped p-well, and performing ion implantation using a second dose to form the standard p-well. The second dose is the difference of the dopant concentrations of the lightly doped p-well and the standard p-well. Other high voltage devices can also be built by incorporating the lightly doped p-well structure.

Abstract: A semiconductor device includes: a semiconductor substrate; an IGBT element including a collector region; a FWD element including a cathode region adjacent to the collector region; a base layer on the substrate; multiple trench gate structures including a gate electrode. The base layer is divided by the trench gate structures into multiple first and second regions. Each first region includes an emitter region contacting the gate electrode. Each first region together with the emitter region is electrically coupled with an emitter electrode. The first regions include collector side and cathode side first regions, and the second regions include collector side and cathode side second regions. At least a part of the cathode side second region is electrically coupled with the emitter electrode, and at least a part of the collector side second region has a floating potential.

Abstract: A semiconductor device is provided which includes a semiconductor substrate having a first portion and a second portion, transistors formed in the first portion of the substrate, each transistor having a gate structure with a high-k dielectric and a metal gate, a device element formed in the second portion of the substrate, the device element being isolated by an isolation region, and a polishing stopper formed adjacent the isolation region and having a surface that is substantially planar with a surface of the gate structures of the transistors in the first region.