Abstract: A biCMOS device including a bipolar transistor and a Polysilicon/Insulator/Polysilicon (PIP) capacitor is disclosed. A biCMOS device may have a relatively low series resistance at a bipolar transistor. A bipolar transistor may have a desirable amplification rate.

Abstract: The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

Abstract: A nonvolatile memory cell that can be mounted in a CMOS manufacturing process, and is capable of implementing high level of programming, reading and erasing ability. The memory cell is configured by a MOS transistor including two N-type first impurity diffusion layers formed separately on a P-type semiconductor substrate, and a first gate electrode formed above a first cannel region sandwiched by both diffusion layers through a first gate insulation film, a first capacitor comprising P-type second impurity diffusion layers formed on a well, and a second gate electrode formed above the diffusion layer through a second gate insulation film, and a second capacitor comprising the well adjacent to the second impurity diffusion layer, and a third gate electrode formed above the well through a third gate insulation film, wherein a different voltage can be applied to each of the capacitors.

Abstract: A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.

Abstract: A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

Abstract: A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.

Abstract: A capacitor assembly (82) is formed on a substrate (20). The capacitor assembly a first conductive plate (38) and a second conductive plate (60) formed over the substrate such that the second conductive plate is separated from the first conductive plate by a distance. A conductive trace (40) is formed over the substrate that is connected to the first conductive plate and extends away from the capacitor assembly. A conductive shield (62) is formed over at least a portion of the conductive trace that is separated from the first and second conductive plates to control a fringe capacitance between the second conductive plate and the conductive trace.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: An electrostatic discharge protection device comprising a multi-finger gate, a first lightly doped region of a second conductivity, a first heavily doped region of the second conductivity, and a second lightly doped region of the second conductivity. The multi-finger gate comprises a plurality of fingers mutually connected in parallel over an active region of a first conductivity. The first lightly doped region of a second conductivity is disposed in the semiconductor substrate and between two of the fingers. The first heavily doped region of the second conductivity is disposed in the first lightly doped region of the second conductivity. The second lightly doped region of the second conductivity is beneath and adjoins the first lightly doped region of the second conductivity.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: The present invention includes a bipolar ESD device for protecting an integrated circuit from ESD damage. The bipolar ESD device includes a collector connected to a terminal of the integrated circuit, a floating base, and a grounded emitter. When an ESD pulse hits the terminal of the integrated circuit, the PN junction between the emitter and the base becomes forward biased. The forward biasing of the emitter-base PN junction in turn causes carriers to be injected into the collector-base junction, triggering the bipolar ESD device to turn on to discharge the ESD pulse. The trigger voltage of the bipolar ESD device is a fraction of a breakdown voltage of the collector-base PN junction and can be modified by adjusting a base length of the bipolar ESD device, a junction depth of the collector, or a dopant concentration in the base.

Abstract: The present invention discloses a high voltage and high frequency poly emitter bipolar structure with improved breakdown voltage performance. The advantage of the poly emitter bipolar structures is that the SOD coating layer can improve the breakdown voltage of a capacitor structure higher to be 6-8 volts. In addition, the poly emitter bipolar structure having the inter-level dielectric layer deposited by PECVD on the emitter and collector by optimizing PECVD deposition process condition to adjust the charge in the oxide of inter-level dielectric layer has a breakdown voltage higher than 30 volts.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: A band pass filter (114) is formed on an integrated circuit (IC) chip (102). Such band pass filter (114) may be used in a RF or wireless communication device, such as a mobile phone or a personal data assistant (PDA). The band pass filter (114) includes a transformer (202 and 204) made of a pair of metallic spirals formed on the IC chip. The metallic spirals may have substantially square or rectangular overall shape, and may be fabricated using copper. The metallic spirals may be co-planar and inter-wound or may be stacked, one on top of the other, and separated by a dielectric layer. The transformer (202 and 204) is capable of receiving an input signal, and providing high pass filtering to the input signal. The band pass filter (114) also includes a capacitor (226, 2; 230 and 232) that is capable of receiving the input signal and providing low pass filtering in conjunction with an inductance of the transformer (202 and 204).