Vertical Bipolar Transistor In Combination With Resistor Or Capacitor Only (epo) Patents (Class 257/E27.021)
  • Patent number: 11817353
    Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: November 14, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
  • Patent number: 8587094
    Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisao Kawasaki
  • Patent number: 8319286
    Abstract: A system and method for electrostatic discharge protection. The system includes a first transistor including a first drain, a second transistor including a second drain, and a resistor including a first terminal and a second terminal. The first terminal is coupled to the first drain and the second drain. Additionally, the system includes a third transistor coupled to the second terminal and a protected system. The third transistor includes a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a third drain. The protected system includes a fourth transistor, and the fourth transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a fourth drain.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Ting Chieh Su, Min Chie Jeng, Chin Chang Liao, Jun Cheng Huang
  • Patent number: 8138574
    Abstract: A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Chung Hon Lam, Bipin Rajendran
  • Publication number: 20100230719
    Abstract: In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 16, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi SAWAHATA
  • Patent number: 7791169
    Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
  • Patent number: 7768004
    Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: August 3, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideomi Shintaku
  • Publication number: 20090032906
    Abstract: An electro static discharge device includes a semiconductor body. The semiconductor body includes a first surface, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged on the first semiconductor region and a third semiconductor region of the first conductivity type. The third semiconductor region is isolated from the first semiconductor region by the second semiconductor region. A resistor structure is arranged in the semiconductor body and comprises at least one trench structure. The resistor structure is arranged at least in the second semiconductor region and provides a high-resistance electrical connection between a first portion and a second portion of the second semiconductor region.
    Type: Application
    Filed: July 30, 2007
    Publication date: February 5, 2009
    Applicant: Infineon Technologies Austria AG
    Inventors: Thomas Ostermann, Nicola Vannucci