Abstract: A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.

Abstract: An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate.

Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract: An electrical device includes a semiconductor material. The semiconductor material includes a first region of the semiconductor material having a first conductivity type, a second region of the semiconductor material having a second conductivity type complementary to the first conductivity type and an intermediate region of the semiconductor material between the first region and the second region. The first and second regions lie next to each other the intermediate region so as to form a diode structure. A shape of the intermediate region tapers from the first region to the second region.

Abstract: In a semiconductor device including a capacitor which has an upper electrode, a polycrystalline silicon layer on the upper electrode, and a metallic member on the polycrystalline silicon layer, the polycrystalline silicon layer includes germanium so that an upper portion of the polycrystalline silicon layer is lower than a lower portion thereof in a concentration of germanium.

Abstract: The present invention provides a semiconductor structure, including a substrate, a first TSV, an inductor and a capacitor. The first TSV is disposed in the substrate and has a first signal. The inductor is disposed in the substrate. The capacitor is electrically connected to the inductor to form an LC circuit to bypass the noise from the first signal. The present invention further provides a method of reducing the signal noise in a semiconductor structure.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.

Abstract: A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.

Abstract: A semiconductor device includes a semiconductor body with a base layer and a field shaping zone of a first conductivity type. The base layer extends parallel to a back surface of the semiconductor body in a central portion and into an edge portion that surrounds the central portion. The field shaping zone is formed in the edge portion and has a maximum dopant concentration exceeding at least three times a maximum dopant concentration in the base layer. A back side metal structure directly adjoins the back surface in the central portion and extends over the edge portion. A dielectric structure is between the back side metal structure and the field shaping zone. Leakage current mechanisms reducing the reverse blocking capabilities are reduced.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a capacitor over a workpiece. The capacitor includes a bottom electrode, a capacitor dielectric disposed over the bottom electrode, and a top electrode disposed over the capacitor dielectric. A portion of the bottom electrode and a portion of the top electrode are removed proximate edges of the capacitor dielectric.

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: An integrated circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; an insulation layer over the substrate; a resistor over the insulation layer; a thermal gate over the resistor; and a heat sink connected to the thermal gate via a substrate contact, the heat sink adapted to receive thermal energy from the resistor via the thermal gate.

Abstract: In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor structure disposed on the substrate. The capacitor structure includes a first conductive component; a second conductive component and a third conductive component symmetrically configured on opposite sides of the first conductive component. The first, second and third conductive components are separated from each other by respective dielectric material.

Abstract: The present disclosure is directed to a device and a method for forming a precision temperature sensor switch with a Wheatstone bridge configuration of four resistors and a comparator. When the temperature sensor detects a temperature above a threshold, the switch will change states. The four resistors in the Wheatstone bridge have the same resistance, with three of the resistors having a low temperature coefficient of resistance and the fourth resistor having a high temperature coefficient of resistance. As the temperature increases, the resistance of the fourth resistor will change. The change in resistance of the fourth resistor will change a voltage across the bridge. The voltage across the bridge is coupled to the comparator and compares the voltage with the threshold temperature, such that when the threshold temperature is exceeded, the comparator switches the output off.

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract: Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a second insulation layer on the first insulation layer, the second insulation layer including a metal head pattern, a thin film resistor pattern on the metal head pattern, a third insulation layer on the thin film resistor pattern, an upper metal line on the third insulation layer, a first via passing through the first, second, and third insulation layers to connect the lower metal line to the upper metal line, and a second via passing through the third insulation layer and the thin film resistor pattern to connect the metal head pattern to the upper metal line.

Abstract: The present invention provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor.

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Abstract: The non-volatile memory device may include a substrate, a plurality of first signal lines on the substrate in a vertical direction, a plurality of memory cells having ends connected to the plurality of first signal lines, a plurality of second signal lines perpendicular to the plurality of first signal lines on the substrate and each connected to other ends of the plurality of memory cells, and a plurality of selection elements on the substrate and connected to at least two of the plurality of first signal lines.

Abstract: An ESD protection circuit includes a pad of an IC, circuitry coupled to the pad for buffering data, an RC power clamp on the IC, and first and second silicon controlled rectifier (SCR) circuits. The RC power clamp is coupled between a positive power supply terminal and a ground terminal. The first SCR circuit is coupled between the pad and the positive power supply terminal. The first SCR circuit has a first trigger input coupled to the RC power clamp circuit. The second SCR circuit is coupled between the pad and the ground terminal. The second SCR circuit has a second trigger input coupled to the RC power clamp circuit. At least one of the SCR circuits includes a gated diode configured to selectively provide a short or relatively conductive electrical path between the pad and one of the positive power supply terminal and the ground terminal.

Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.

Abstract: A system and method for improving the prompt dose radiation response of mixed-signal integrated circuits is disclosed. An internal analog circuit inside a mixed-signal integrated circuit generates an internal analog reference voltage that has been used for various purposes in the integrated circuit. At least one external capacitor is added either internal or external to a device package of the integrated circuit. The external capacitor reduces any change in the internal reference voltage due to prompt dose radiation by stabilizing the internal reference voltage and thus improves prompt dose radiation response of mixed-signal integrated circuits. A much greater value of capacitance may be provided without increase in dielectric rupture suceptability or decrease in manufacturing yield which may be associated with added on-chip capacitance. This increased capacitance primarily reduce the amount of disturbance caused to the internal node during a prompt dose radiation event.

Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.

Abstract: To reduce the radio frequency (RF) losses associated with high RF loss plating, such as, for example, Nickel/Palladium/Gold (Ni/Pd/Au) plating, an on-die passive device, such as a capacitor, resistor, or inductor, associated with a radio frequency integrated circuit (RFIC) is placed in an RF upper signal path with respect to the RF signal output of the RFIC. By placing the on-die passive device in the RF upper signal path, the RF current does not directly pass through the high RF loss plating material of the passive device bonding pad.

Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.

Abstract: A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching.

Abstract: In one general aspect, an apparatus can include a barrier diode including a refractory metal layer coupled to a semiconductor substrate including at least a portion of a PN junction and the apparatus can include an overcurrent protection device operably coupled to the barrier diode.

Abstract: A hacking detecting device includes a metal line capacitor, a charge providing unit, a charge storing unit and a hacking deciding unit. The metal line capacitor has a first metal line and a second metal line. The charge providing unit periodically charges the metal line capacitor. The charge storing unit accumulates charges periodically stored in the metal line capacitor, and generates an output voltage corresponding to an amount of the accumulated charges. The hacking deciding unit determines whether the metal line capacitor is exposed based on the output voltage of the charge storing unit.

Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract: In a high voltage ESD protection structure with a gate voltage reference and low impedance load, the CDM robustness of the structure is improved by including a gate resistor and a reverse path diode.

Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.

Abstract: A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals.

Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.

Abstract: A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces, is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.

Abstract: Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.

Abstract: A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. In an MMIC 100 in which an FET as an active element and the MIM capacitor are formed on a GaAs substrate 10, for example, a source electrode 16a and a drain electrode 16b, which are ohmic electrodes of the FET, are manufactured simultaneously with a lower electrode 16c of the MIM capacitor. Here the electrodes are formed with the same metal.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: The present invention relates to an electric component comprising at least one first MIM capacitor having a ferroelectric insulator with a dielectric constant of at least 100 between a first capacitor electrode of a first electrode material and a second capacitor electrode of a second electrode material. The first and second electrode materials are selected such that the first MIM capacitor exhibits, as a function of a DC voltage applicable between the first and second electrodes, an asymmetric capacity hysteresis that lets the first MIM capacitor, in absence of the DC voltage, assume one of at least two possible distinct capacitance values, in dependence on a polarity of a switching voltage last applied to the capacitor, the switching voltage having an amount larger than a threshold-voltage amount. The invention is applicable for ESD sensors, memories and high-frequency devices.

Abstract: The invention relates to an electronic device provided with an electronic component which comprises an integrated circuit arrangement including a semiconducting substrate, active components, and passive components such as capacitors and resistors. The resistors comprise materials of a high resistivity and can be manufactured with resistance values which lie within a narrow tolerance range. The invention further relates to a transmitter, a receiver, an electronic component, a peripheral circuit, a current supply circuit, a filter module, and an integrated circuit arrangement.