Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a metal-insulator-metal capacitor and methods of manufacture. The structure includes: a first buffer contact on a substrate; a second buffer contact on the substrate, the second buffer contact being on a same wiring level as the first buffer contact; a resistive film contacting the first buffer contact and the second buffer contact, the resistive film extending on the substrate between the first buffer contact and the second buffer contact; and electrical contacts landing on both the first buffer contact and the second buffer contact, but not directly contacting with the resistive film.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip which includes a semiconductor integrated circuit provided in an insulator, a first pad a pad having an upper surface of which is exposed via an opening formed in the insulator, and capacitors provided in a capacitor region of the semiconductor chip under the pad. The capacitors are provided in the capacitor region to satisfy a rule of a coverage. And contacts respectively connected to two electrodes of the capacitors are provided at positions that do not vertically overlap the opening.

Abstract: A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

Abstract: Some embodiments relate a capacitor array arranged on a semiconductor substrate. The capacitor array includes an array of unit capacitors arranged in a series of rows and columns. An interconnect structure couples unit capacitors of the array to establish a plurality of capacitor elements. The respective capacitor elements have different numbers of unit capacitors and different corresponding capacitances. In establishing the plurality of capacitor elements, the interconnect structure couples unit capacitors of the array in substantially identical sub-arrays tiled over the semiconductor substrate. Other methods and devices are also disclosed.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material.

Abstract: A current sense resistor integrated with an integrated circuit die where the integrated circuit die is housed in a flip-chip semiconductor package includes a metal layer formed over a passivation layer of the integrated circuit die where the metal layer having an array of metal pillars extending therefrom. The metal pillars are electrically connected to a first leadframe portion and a second leadframe portion of the semiconductor package where the first leadframe portion and the second leadframe portion are electrically isolated from each other and physically separated by a separation of a first distance. The current sense resistor is formed in a portion of the metal layer spanning the separation between the first and second leadframe portions, the first and second leadframe portions forming terminals of the current sense resistor.

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract: An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening.

Abstract: A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.

Abstract: A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

Abstract: The present application discloses a semiconductor integrated circuit including a substrate having electrical devices formed thereon, a local interconnection layer formed over the substrate, and a global interconnection layer formed over the local interconnection layer. The local interconnection layer has a first set of conductive structures arranged to electrically connect within the individual electrical devices, among one of the electrical devices and its adjacent electrical devices, or vertically between the devices and the global interconnection layer. At least one of the first set of conductive structures is configured to have a resistance value greater than 50 ohms. The global interconnection layer has a second set of conductive structures arranged to electrically interconnect the electrical devices via the first set conductive structures.

Abstract: A method for forming an embedded capacitor structure is provided. Firstly, a first dielectric layer having a trench therein on a substrate is provided. A capacitor structure is formed on the bottom surface of the trench. The capacitor structure includes a first metal layer, a capacitance-insulating layer and a second metal layer and the portion surface of the first metal layer on the bottom surface of the trench is exposed. A cap layer is formed on the top surface and the inner surface of the trench and on the capacitor structure. A second dielectric layer is formed on the cap layer. The portion of second dielectric layer and the portion of the cap layer are removed to form a plurality of contact windows therein, and the portion surface of the first metal layer and the portion surface of the second metal layer are exposed by the plurality of contact windows.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element disposed in the semiconductor substrate, a guard ring surrounding at least a part of a periphery of the semiconductor element, a guard ring terminal coupled with the guard ring, a power supply line divided from a line coupled with a power source and applying a first constant voltage to the semiconductor element based on a voltage generated by the power source, a guard ring terminal fixation line divided from the line coupled with the power source and applying a second constant voltage to the guard ring terminal, a bypass capacitor disposed on the guard ring terminal fixation line so as to be coupled in parallel with the guard ring, and a resistor disposed on the guard ring terminal fixation line between the power source and the bypass capacitor.

Abstract: An integrated circuit having a place-efficient capacitor includes a lower capacitor electrode having a surface area comprised of an inner surface area of a partial opening and a via opening formed in a patterned dielectric layer on a semiconductor substrate, a capacitor insulating layer overlying the lower capacitor electrode, and an upper capacitor electrode including a metal fill material filling the partial opening and the via opening and having a surface area that includes the inner surface area of the partial opening and via opening.

Abstract: Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Abstract: A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.

Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.

Abstract: Capacitors and methods of forming semiconductor device capacitors are disclosed. Trenches are formed to define a capacitor bottom plate in a doped upper region of a semiconductor substrate, a dielectric layer is formed conformally over the substrate within the trenches, and a polysilicon layer is formed over the dielectric layer to define a capacitor top plate. A guard ring region of opposite conductivity and peripheral recessed areas may be added to avoid electric field crowding. A central substrate of lower doping concentration may be provided to provide a resistor in series below the capacitor bottom plate. A series resistor may also be provided in a resistivity region of the polysilicon layer laterally extending from the trenched area region. Contact for the capacitor bottom plate may be made through a contact layer formed on a bottom of the substrate.

Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: In a semiconductor integrated circuit device including a digital circuit region in which a digital circuit is formed, and an analog circuit region in which an analog circuit is formed, the analog circuit region is separated into an active element region in which an active element of the analog circuit is formed, and a resistive and capacitive element region in which a resistor or a capacitor of the analog circuit is formed, the resistive and capacitive element region is arranged in a region adjacent to the digital circuit region, and the active element region is arranged in a region separated from the digital circuit region.

Abstract: Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A method and structure for a semiconductor device which provides for an etch of a metal layer such as an interconnect layer which does not affect a thinner layer such as a thin film resistor (TFR) layer, such as a circuit resistor. In one embodiment, a TFR resistor layer is protected by a patterned protective layer during an etch of the metal layer, and provides an underlayer for the metal layer. In another embodiment, the TFR layer is formed after providing the patterned metal layer. The metal layer can provide, for example, end caps for the circuit resistor.

Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.

Abstract: An integrated circuit includes a semiconductor body of a first conductivity type. The semiconductor body includes a first semiconductor zone of a second conductivity type opposite the first conductivity type. The first semiconductor zone extends to a surface of the semiconductor body. A second semiconductor zone of the first conductivity type is embedded in the first semiconductor zone and extends as far as the surface. A third semiconductor zone of the second conductivity type at least partly projects from the first semiconductor zone along a lateral direction running parallel to the surface. A contact structure provides an electrical contact with the first and second semiconductor zones at the surface. The second semiconductor zone is arranged, along the lateral direction, between the part of the third semiconductor zone which projects from the first semiconductor zone and a part of the contact structure in contact with the first semiconductor zone.

Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

Abstract: A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract: A semiconductor integrated circuit has a plurality of capacitor cells, and each capacitor cell has an upper electrode and a lower electrode. These electrodes are respectively connected to an upper electrode wiring and a lower electrode. When, for example, the upper electrode is connected to the upper electrode wiring and the electrode wiring is located at a side of the lower electrode of another capacitor cell or a side of the lower electrode wiring connecting these electrodes, a shield wiring is provided between the upper electrode wiring and the adjacently-located lower electrode of the other capacitor cell or between the upper electrode wiring and the adjacently-located lower electrode wiring. Thus, with this shield wiring, the capacitance coupling between each wiring of the capacitor cells and each upper electrode or each lower electrode of the capacitor cells are effectively suppressed.

Abstract: A method for forming a thin film resistor includes providing a substrate having a transistor region and a thin film resistor region defined thereon, sequentially forming a dielectric layer, a metal layer and a first hard mask layer on the substrate, patterning the first hard mask layer to form at least a thin film resistor pattern in the thin film resistor region, sequentially forming a polysilicon layer and a second hard mask layer on the substrate, patterning the second hard mask layer to form at least a gate pattern in the transistor region, and performing an etching process to form a gate and a thin film resistor respectively in the transistor region and the thin film resistor region.

Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.

Abstract: An integrated circuit package for magnetic capacitor including a substrate, an integrated circuit and a magnetic capacitor unit is disclosed. The substrate has a first surface and an opposite second surface. The integrated circuit is connected to the second surface of the substrate. The magnetic capacitor unit has a positive terminal and a negative terminal connected to the substrate.

Abstract: An explanation is given of, inter alia, a circuit arrangement in which an intermediate layer (160) made of a dielectric material is arranged between two metal layers (102 and 104). The intermediate layer (160) is designed in such a way that the capacitance per unit area between the connection layers (102, 104) is greater than 0.5 fF/?m2.

Abstract: In a semiconductor device, a plurality of triple-stacked structures all having the same structure are provided. Each of the triple-stacked structures includes one lower electrode layer, at least one upper electrode layer and one dielectric layer sandwiched by the lower electrode layer and the upper electrode layer.

Abstract: A disclosed capacitor sheet attached to an electronic apparatus comprises: a laminated body; a first penetration electrode penetrating the laminated body, the first penetration electrode being electrically connected to a terminal electrode of the electronic apparatus; a second penetration electrode disposed at an arrangement position different from that of the first penetration electrode on the laminated body, the second penetration electrode being electrically insulated from the first penetration electrode and penetrating the laminated body; at least one first conductor thin film electrically connected to the first penetration electrode and insulated from the second penetration electrode; and at least one second conductor thin film disposed so as to face the first conductor thin film via a dielectric layer, the second conductor thin film being electrically connected to the second penetration electrode and insulated from the first penetration electrode.

Abstract: A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.

Abstract: A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Abstract: A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell.

Abstract: A biosensor chip (100) for detecting biological particles, the biosensor chip (100) comprising a sensor active region (101) being sensitive for the biological particles and being arranged in a Back End of the Line portion (102) of the biosensor chip (100).

Abstract: A device 20 includes substrates 22 and 24 coupled to form a volume 32 between the substrates. A surface 28 of the substrate 22 faces a surface 30 of the substrate 24. A metal-insulator-metal capacitor 34 is formed on one of the surfaces 28 and 30. A conductive element 58 spans between a top electrode 56 of the capacitor 34 and the other surface 28 and 30. Vias 64 and 66 extend through the substrate 22 and are electrically interconnected with the conductive element 58 and a bottom electrode 52 of the capacitor 34. Another device 72 includes an underpass transmission line 92 formed on a surface 80 of a substrate 74 within a volume 84 formed between the substrate 74 and another substrate 76. The line 92 underlies an integrated device 96 formed on a surface 78 of the substrate 74.

Abstract: The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A semiconductor integrated circuit includes a substrate, an oxide layer formed on an upper surface of the substrate, a plurality of polysilicon members arranged at constant intervals in a matrix on an upper surface of the oxide layer and including at least one first polysilicon member and a plurality of second polysilicon members, and a diffusion layer formed in the substrate under the first polysilicon member and electrically coupled to an interconnect for supplying a first power supply voltage, wherein the first polysilicon member is situated at an outermost periphery of the matrix and electrically coupled to an interconnect for supplying a second power supply voltage, and the plurality of second polysilicon members are situated inside the outermost periphery of the matrix.

Abstract: A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).