Vertical Bipolar Transistor In Combination With Capacitor Only (epo) Patents (Class 257/E27.042)
  • Patent number: 8921911
    Abstract: A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: December 30, 2014
    Assignee: Rexchip Electronics Corporation
    Inventors: Pin-Yuan Yu, Yi-Chun Shao, Chien-Hua Chu
  • Patent number: 8513773
    Abstract: A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 7586130
    Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Takeshi Takagi