Abstract: An integrated circuit (IC) comprises a rectifier/regulator circuit coupled to receive an ac source voltage and output a regulated dc voltage. The rectifier/regulator circuit includes first and second switching elements that provide charging current when enabled. The first and second switching elements do not provide charging current when disabled. A sensor circuit is coupled to sense the regulated dc voltage and generate a feedback control signal coupled to the rectifier/regulator circuit that enables the first and second switching elements when the regulated do voltage is above a target voltage, and disables the first and second switching elements when the regulated do voltage is below the target voltage.

Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.

Abstract: A method of forming a stacked low temperature diode and related devices. At least some of the illustrative embodiments are methods comprising forming a metal interconnect disposed within an inter-layer dielectric. The metal interconnect is electrically coupled to at least one underlying integrated circuit device. A barrier layer is deposited on the metal interconnect and the inter-layer dielectric. A semiconductor layer is deposited on the barrier layer. A metal layer is deposited on the semiconductor layer. The barrier layer, the semiconductor layer, and the metal layer are patterned. A low-temperature anneal is performed to induce a reaction between the patterned metal layer and the patterned semiconductor layer. The reaction forms a silicided layer within the patterned semiconductor layer. Moreover, the reaction forms a P-N junction diode.

Abstract: A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

Abstract: A molded resin product or the like that is provided with a phosphor layer made of gel-like or rubber-like resin that can maintain its shape for a long period and that can be implemented easily. The molded resin product (phosphor layer 7) includes a resin member 17 made of a gel-like or rubber-like translucent resin including a phosphor material. The resin member 17 includes a shape maintaining member 19 that is formed in a lattice shape by line-like members 20 that are made of a material having a higher elasticity modulus than the resin member 17. The molded resin product (phosphor layer 7) is in the shape of a dome. The translucent resin is made of, for example, silicon resin, and the resin member 17 is gel-like.

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

Abstract: A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.

Abstract: A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin.

Abstract: The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Abstract: An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated circuit also includes a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality of diodes. The first node is located between a first diode of the first plurality of diodes and a last diode of the first plurality of diodes, and the second node is located between a first diode of the second plurality of diodes and a last diode of the second plurality of diodes.

Abstract: A light-emitting diode (LED) structure fabricated with a SixNy layer responsible for providing increased light extraction out of a surface of the LED is provided. Such LED structures fabricated with a SixNy layer may have increased luminous efficiency when compared to conventional LED structures fabricated without a SixNy layer. Methods for creating such LED structures are also provided.

Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.

Abstract: A semiconductor device comprising a plurality of regions of semiconductor material forming a junction at an interface there-between, the junction including a depletion region having a width which varies spatially in at least one direction along the depletion region. Without limitation, the spatial variation in depletion region width is provided by ionised dopants having a concentration which varies spatially along said at least one direction. Alternatively, or in addition, the spatial variation in depletion region width is achieved by varying the thickness of the region(s) of semiconductor spatially along said at least one direction, for example by creating a plurality of cells within said region(s) devoid of said semiconductor material. A method of fabricating a semiconductor device comprising the step of varying the width of the depletion region spatially there-within in at least one direction along the depletion region.

Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.

Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. The first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like.

Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.

Abstract: A protection diode includes a semiconductor substrate having a first region, a second region surrounding the first region, and a third region surrounding the second region; a first insulation layer disposed between the second region and the third region; a first conductive type semiconductor portion disposed in the third region; a second conductive type semiconductor portion disposed in the second region; and a capacity reduction layer disposed in the first region.

Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.

Abstract: A semiconductor diode includes a semiconductor substrate having a lightly doped region with a first conductivity type therein. A first heavily doped region with a second conductivity type opposite to the first conductivity type is in the lightly doped region. A second heavily doped region with the first conductivity type is in the lightly doped region and is in direct contact with the first heavily doped region. A first metal silicide layer is on the semiconductor substrate and is in direct contact with the first heavily doped region. A second metal silicide layer is on the semiconductor substrate and is in direct contact with the second heavily doped region. The second metal silicide layer is spaced apart from the first metal silicide layer.

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: The cell size is reduced and device reliability is improved for a semiconductor device including plural transistors making up a multi-channel output circuit. In a multi-channel circuit configuration, a group of transistors having a common function of plural channels are surrounded by a common trench for insulated isolation from another group of transistors having another function. The collectors of mutually adjacent transistors on the high side are commonly connected to a VH power supply, whereas the emitters of mutually adjacent transistors on the low side are commonly connected to a GND power supply.

Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

Abstract: A resistance changing device includes a resistive layer of a hetero structure interposed between a lower electrode and an upper electrode, and including a plurality of resistive material layers, each having a different resistivity, stacked therein, wherein resistivities of the resistive material layers decrease from the lower electrode toward the upper electrode. Since the resistive layer has a hetero structure in which a plurality of resistive material layers, each having a different resistivity, are stacked in such a manner that the resistivity decreases as it goes from the lower electrode to the upper electrode, it is possible to improve the distributions of the set/reset voltage and the set/reset current, while reducing a reset current of a resistance changing device at the same time.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract: The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.

Abstract: A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A semiconductor apparatus includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a semiconductor film provided on the insulating film. The semiconductor substrate includes a region of a first current path including at least one diode, the semiconductor film includes a region of a second current path including at least one diode, the first current path and the second current path are connected in parallel to each other, the region of the first current path includes at least part of an area directly below the region of the second current path, and the first current path has a higher resistance than the second current path.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.

Abstract: Techniques for combining nanotechnology with photovoltaics are provided. In one aspect, a method of forming a photovoltaic device is provided comprising the following steps. A plurality of nanowires are formed on a substrate, wherein the plurality of nanowires attached to the substrate comprises a nanowire forest. In the presence of a first doping agent and a first volatile precursor, a first doped semiconductor layer is conformally deposited over the nanowire forest. In the presence of a second doping agent and a second volatile precursor, a second doped semiconductor layer is conformally deposited over the first doped layer. The first doping agent comprises one of an n-type doping agent and a p-type doping agent and the second doping agent comprises a different one of the n-type doping agent and the p-type doping agent from the first doping agent. A transparent electrode layer is deposited over the second doped semiconductor layer.

Abstract: A light-emitting device operating on a high drive voltage and a small drive current. LEDs (1) are two-dimensionally formed on an insulating substrate (10) of e.g., sapphire monolithically and connected in series to form an LED array. Two such LED arrays are connected to electrodes (32) in inverse parallel. Air-bridge wiring (28) is formed between the LEDs (1) and between the LEDs (1) and electrodes (32). The LED arrays are arranged zigzag to form a plurality of LEDs (1) to produce a high drive voltage and a small drive current. Two LED arrays are connected in inverse parallel, and therefore an AC power supply can be used as the power supply.

Abstract: A diode, includes a semiconductor substrate, a first region doped with a first dopant type in the substrate, a second region doped with a second dopant type in the substrate, a first well of the first dopant type in the substrate and surrounding the first region and the second region, and a second well of the second dopant type in the substrate connecting the first region and the second region. The first dopant type is opposite the second dopant type.

Abstract: A serially-connected diode pair made of diodes having a high withstand voltage and a low on-resistance is formed based on a high withstand voltage vertical PNP bipolar transistor process technology. Two of the diode pairs are connected in parallel to form a bridge so that there is formed a high-efficiency full-wave rectifier circuit that is free from a leakage current due to a parasitic transistor. The serially-connected diode pair is formed by connecting a diode composed of a P type semiconductor substrate, that makes an anode, and an N type buried layer, that makes a cathode, and a diode composed of a P+ type conductive layer, that makes an anode, and an N type epitaxial layer, that makes a cathode, in series with an electrode AC1.

Abstract: In semiconductor devices and methods for their manufacture, the semiconductor devices are arranged as a trench-Schottky-barrier-Schottky diode having a pn diode as a clamping element (TSBS-pn), and having additional properties compared to usual TSBS elements which make possible adaptation of the electrical properties. The TSBS-pn diodes are produced using special manufacturing methods, are arranged in their physical properties such that they are suitable for use in a rectifier for a motor vehicle generator, and are also able to be operated as Z diodes.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of ?m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much.

Abstract: An electrostatic discharge protection circuit has a substrate; a first P-well installed on the substrate and having a first P+-doped region and a first N+-doped region, both of which are connected to ground; a second P-well installed on the substrate and having a second P+-doped region and a second N+-doped region, both of which are connected to a power supply voltage; and a third P-well installed on the substrate and having a third N+-doped region, a third P+-doped region, and a fourth N+-doped region, all of which are for input/output signals.

Abstract: A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area.

Abstract: The present invention relates to an electrostatic discharge diode. The electrostatic discharge diode according to exemplary embodiment of the present invention includes: an N-type well formed on a substrate; an n? region formed on the N-type well; a plurality of p? regions penetrated and formed in the n? region; a plurality of n+ regions penetrated and formed in a first layer in which the n? region and a plurality of the p? regions are formed; a plurality of n+ regions penetrated and formed in a first layer in which the n? region and a plurality of the p? regions are formed; and a plurality of p+ regions penetrated and formed in the first layer, wherein a first n+ region among a plurality of the n+ regions and a first p+ region corresponding to the first n+ region are penetrated and formed in each other region of the corresponding first p? region among a plurality of the p? regions.

Abstract: Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.

Abstract: A semiconductor apparatus includes a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a semiconductor film provided on the insulating film. The semiconductor substrate includes a region of a first current path including at least one diode, the semiconductor film includes a region of a second current path including at least one diode, the first current path and the second current path are connected in parallel to each other, the region of the first current path includes at least part of an area directly below the region of the second current path, and the first current path has a higher resistance than the second current path.

Abstract: A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable structure includes a third region and a fourth region of opposite conductivity types. The first region of the diode and the third region of the programmable structure are electrically connected. In operation, the programmable structure is programmed to a low impedance state when a voltage exceeding a first breakdown voltage of the programmable structure is applied to reverse bias the programmable structure. The programmable element can be used to form a programmable array having very low parasitic capacitance, enabling the realization of a large and ultra fast programmable logic array.

Abstract: An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.

Abstract: A method of forming a MOSFET is provided. The method comprises forming a relatively thin layer of dielectric on a substrate. Depositing a gate material layer on the relatively thin layer of dielectric. Removing portions of the gate material layer to form a first and second gate material regions of predetermined lateral lengths. Introducing a first conductivity type dopant in the substrate to form a top gate using first edges of the first and second gate material regions as masks, Introducing a second conductivity dopant of high dopant density in the substrate to form a drain region adjacent the surface of the substrate using a second edge of the second gate material region as a mask to form a first edge of the drain region, wherein a spaced distance between the top gate and the drain region is determined by the lateral length of the second gate material region.