Combination Of Lateral And Vertical Transistors Only (epo) Patents (Class 257/E27.054)
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Patent number: 9741791Abstract: An integrated circuit is formed by providing a heavily doped substrate of a first conductivity type, forming a lightly doped lower epitaxial layer of the first conductivity type over the substrate, implanting dopants of the first conductivity type into the lower epitaxial layer in an area for a shallow component and blocking the dopants from an area for a deep component, forming a lightly doped upper epitaxial layer over the lower epitaxial layer and activating the implanted dopants to form a heavily doped region. The shallow component is formed over the heavily doped region, and the deep component is formed outside the heavily doped region, extending through the upper epitaxial layer into the lower epitaxial layer.Type: GrantFiled: March 7, 2016Date of Patent: August 22, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: James Fred Salzman, Charles Clayton Hadsell
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Patent number: 8912569Abstract: A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current 56 from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current 56 is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both.Type: GrantFiled: July 27, 2012Date of Patent: December 16, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Vishal P. Trivedi
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Publication number: 20130328170Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
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Patent number: 8530942Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.Type: GrantFiled: March 17, 2011Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Tsubasa Yamada
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Patent number: 8409959Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.Type: GrantFiled: March 13, 2007Date of Patent: April 2, 2013Assignee: Micron Technology, Inc.Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
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Patent number: 8399927Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.Type: GrantFiled: February 7, 2012Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu, Yun Shi
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Patent number: 8384150Abstract: A semiconductor device of the present invention includes vertical double diffused MOS transistor. A gate electrode of the vertical double diffused MOS transistor is disposed within a trench formed on a semiconductor substrate and projects from a surface of the semiconductor substrate. On a side surface of the gate electrode, a side wall is formed. On the surface of the semiconductor substrate and a surface of the gate electrode, a metal silicide film is formed.Type: GrantFiled: November 28, 2006Date of Patent: February 26, 2013Assignee: Rohm Co., Ltd.Inventors: Michihiko Mifuji, Ryuta Maruyama, Masaki Hino
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Patent number: 7968940Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.Type: GrantFiled: September 27, 2007Date of Patent: June 28, 2011Assignee: Anpec Electronics CorporationInventor: Florin Udrea
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Publication number: 20100295123Abstract: Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.Type: ApplicationFiled: May 22, 2009Publication date: November 25, 2010Applicants: Macronix International Co., Ltd., International Business Machines CorporationInventors: Hsiang-Lan Lung, Chung H. Lam
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Publication number: 20100213575Abstract: A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter.Type: ApplicationFiled: March 1, 2010Publication date: August 26, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Chih-Ping Chao, Chih-Sheng Chang, Hua-Chou Tseng
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Patent number: 7679121Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.Type: GrantFiled: May 2, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Qiqing Christine Ouyang, Jack Oon Chu
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Patent number: 7586130Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.Type: GrantFiled: February 1, 2006Date of Patent: September 8, 2009Assignee: Panasonic CorporationInventors: Takahiro Kawashima, Tohru Saitoh, Takeshi Takagi
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Patent number: 7569910Abstract: A semiconductor structure is fabricated with two different portions. The first portion forms a first transistor, while the second portion forms a second transistor. Notably, portions of the first transistor also a make up portions of the second transistor. That is, both the first transistor and the second transistor are made of portions of the same structure.Type: GrantFiled: August 30, 2006Date of Patent: August 4, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Mauchung (Frank) Chang, Peiming (Daniel) Chow, Liyang Zhang
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Patent number: 7242050Abstract: A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.Type: GrantFiled: November 13, 2003Date of Patent: July 10, 2007Assignee: Silicon Storage Technology, Inc.Inventors: Bomy Chen, Hieu Van Tran, Dana Lee, Jack Edward Frayer
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Patent number: 7196367Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.Type: GrantFiled: September 30, 2004Date of Patent: March 27, 2007Assignee: Intel CorporationInventors: Dmitri E. Nikonov, George I. Bourianoff