Abstract: Disclosed herein is a solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof, an electric-charge holding region in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out, and a transfer gate having a complete transfer path through which the electric charge accumulated in the photoelectric conversion element is completely transferred into the electric-charge holding region, and an intermediate transfer path through which the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined charge amount is transferred into the electric-charge holding region. The complete transfer path and the intermediate transfer path are formed in different regions.

Abstract: A lens forming method according to the present invention for forming lenses capable of focusing light on a plurality of respective photoelectric conversion sections constituting of a semiconductor apparatus is described. The method includes a lens forming step of processing a lens forming material, in which an average gradient of a ? curve indicating a residual film thickness with respect to the amount of irradiation light is between ?15 and ?0.8 nm·cm2/mJ within the range of a residual film ratio of 10 to 50% or within the range of the amount of irradiation light of 55 to 137 mJ/cm2 into a lens surface shape, using a photomask with an optical transmittance that is varied according to a lens surface shape, as an exposure mask.

Abstract: A solid-state imaging device includes: a semiconductor substrate having a plurality of vertical transfer channel regions and a plurality of photoelectric conversion regions arranged in a matrix; a plurality of vertical transfer electrodes, each constructed of a gate electrode and a first metal light-shielding film, formed via a gate insulating film; a transparent insulating film formed in gaps existing between the vertical transfer electrodes above the vertical transfer channel regions; and a second metal light-shielding film formed via a first interlayer insulating film to cover at least the vertical transfer channel regions.

Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.

Abstract: There is provided an image pickup device, including a photoelectric conversion element converting light into charges, a transfer gate for transferring the converted charges to a floating node, a source follower transistor for outputting a signal based on a voltage of the floating node to a signal line, and a clip circuit clipping the signal line at a first voltage and a second voltage.

Abstract: A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded.

Abstract: An image sensor and a method for manufacturing the same are disclosed. The image sensor can include a semiconductor substrate that includes photodiodes arranged for each unit pixel; an interlayer dielectric layer and metal wirings disposed on the semiconductor substrate; and a photorefractive unit that is formed on the periphery of an optical path incident on the photodiodes. The photorefractive unit has a lower refractive index than the interlayer dielectric layer. The slantly incident light can be incident on the photodiodes, while maintaining the slanted optical path as it is. The light sensitivity of the photodiodes can be improved, thereby improving image quality.

Abstract: A nonvolatile semiconductor memory device having a source-side-injected split-gate type of nonvolatile memory cell which can be formed by a one-layer polysilicon CMOS process is provided. A memory cell includes a first memory cell unit including first and second diffusion regions formed on a semiconductor substrate surface, and first and second gate electrodes separately formed through a gate insulation film on a first channel region between the first and second diffusion regions, a second memory cell unit including third and fourth diffusion regions formed on the semiconductor substrate surface, and a third gate electrode formed through a gate insulation film on a second channel region between the third and fourth diffusion regions, and a control terminal. The first to third gate electrodes are formed of the same electrode material layer. The second and third gate electrodes are electrically connected to form a floating gate capacitively coupled to the control terminal.

Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: A light detecting element 1 including an element formation layer 22 which contains a well region 31. A surface electrode 25 is formed on the layer 22 through an insulating layer 24. The region 31 contains an electron holding region 32. The region 32 contains a hole holding region 33. The layer 24 contains a control electrode 26 facing the region 33 through the layer 24. Electrons and holes are generated at the layer 22. There are two selected states. In one state, by controlling each electric potential applied to the electrodes 25, 26, electrons are gathered at the region 32, while holes are held at the region 33. In another state, recombination is stimulated between the electrons and the holes. After the recombination, the remaining electrons are picked out as received light output.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.

Abstract: An integrated circuit device may include a first insulating layer on a substrate with an opening through the first insulating layer. A conductive layer may be on the first insulating layer with the first insulating layer between the conductive layer and the substrate and with the conductive layer set back from the opening. A second insulating layer may be on the conductive layer with the conductive layer between the first and second insulating layers. The second insulating layer may be set back from the opening, and a sidewall of the conductive layer adjacent the opening may be recessed relative to a sidewall of the second insulating layer adjacent the opening. An insulating spacer on portions of the first insulating layer may surround the opening, and the insulating spacer may be on the sidewall of the second insulating layer adjacent the opening so that the insulating spacer is between the sidewall of the second conductive layer and the opening.

Abstract: A CMOS image sensor includes a pinned photodiode and a transfer gate that are formed using a thick mask that is self-aligned to at least one edge of the polysilicon gate structure to facilitate both the formation of a deep implant and to provide proper alignment between the photodiode implant and the gate. In one embodiment a drain side implant is formed concurrently with the deep n-type implant of the photodiode. After the deep implant, the mask is removed and a shallow p+ implant is formed to complete the photodiode. In another embodiment, the polysilicon is etched to define only a drain side edge, a shallow drain side implant is performed, and then a thick mask is provided and used to complete the gate structure, and is retained during the subsequent high energy implant. Alternatively, the high energy implant is performed prior to the shallow drain side implant.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.

Abstract: A sensor includes an array of pixels organized in rows and columns and a plurality of metal busses overlaying the array of pixels. A first column of pixels includes a proximal set of first pixels and a distal set of first pixels separated by a first jog region. A second column of pixels includes a proximal set of second pixels and a distal set of second pixels separated by a second jog region. The first jog region is displaced in a column direction and in a lateral direction transverse to the column direction from the second jog region. A first metal bus is insulatively disposed over both the first and second jog regions.

Abstract: According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.