Including Field-effect Component (epo) Patents (Class 257/E27.081)

  • Patent number: 10916547
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 9, 2021
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 10748600
    Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technologies, Inc.
    Inventors: James S. Rehmeyer, George B. Raad, Debra M. Bell, Markus H. Geiger, Anthony D. Veches
  • Patent number: 10381350
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 10373694
    Abstract: Methods of operating apparatus, and apparatus configured to perform similar methods, include obtaining information indicative of a data value stored in a particular memory cell of an array of volatile memory cells of the apparatus, determining if a power loss to the apparatus is indicated, and, if a power loss to the apparatus is indicated, selectively programming one memory cell of a pair of gate-connected non-volatile memory cells of the apparatus responsive to the information indicative of the data value stored in the particular memory cell. A resulting combination of threshold voltages of the one memory cell of the pair of gate-connected non-volatile memory cells and of the other memory cell of the pair of gate-connected non-volatile memory cells is representative of the information indicative of the data value stored in the particular memory cell.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Rainer Bonitz
  • Patent number: 10366001
    Abstract: Disclosed approaches of processing a circuit design include determining a subset of addresses of a first RAM of the circuit design that are accessed more often than a frequency threshold. A specification of a second RAM is created for the subset of addresses. A decoder circuit is added to the circuit design. The decoder circuit is configured to enable the second RAM and disable the first RAM in response to an input address in the subset of addresses, and to enable the first RAM and disable the second RAM in response to an input address other than addresses in the subset of addresses.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 30, 2019
    Assignee: XILINX, INC.
    Inventors: Nithin Kumar Guggilla, Chaithanya Dudha, Krishna Garlapati, Chun Zhang, Fan Zhang, Anup Kumar Sultania
  • Patent number: 10366740
    Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Sangmin Hwang, Si-Woo Lee
  • Patent number: 10347322
    Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tae H. Kim, Sangmin Hwang, Si-Woo Lee
  • Patent number: 10276241
    Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Patent number: 10236768
    Abstract: The present disclosure relates to a structure which includes a diode-based Dickson charge pump which is configured to use an independent multi-gate device to reduce a threshold voltage of a plurality of transistor diodes during a charging and pumping phase.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventor: Wern Ming Koe
  • Patent number: 10181473
    Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 15, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Wei Feng, Ying-Chiao Wang, Tsung-Ying Tsai, Kai-Ping Chen, Chien-Ting Ho
  • Patent number: 10134869
    Abstract: To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.
    Type: Grant
    Filed: December 4, 2016
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yasufumi Morimoto, Kiyonobu Takahashi, Morihiko Kume
  • Patent number: 10121792
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 10115916
    Abstract: Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
    Type: Grant
    Filed: April 11, 2015
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
  • Patent number: 10007160
    Abstract: An object is to provide a display device that performs accurate display. A circuit is formed using a transistor that includes an oxide semiconductor and has a low off-state current. A precharge circuit or an inspection circuit is formed in addition to a pixel circuit. The off-state current is low because the oxide semiconductor is used. Thus, it is not likely that a signal or voltage is leaked in the precharge circuit or the inspection circuit to cause defective display. As a result, a display device that performs accurate display can be provided.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 26, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki
  • Patent number: 9919147
    Abstract: Electrode arrays for biological implants are disclosed. Electrodes are arranged in such a way so that electrical traces overlap other electrical traces in a separate layer without X shaped crossing, while overlapping to a degree sufficient to prevent dielectric breakdown of the insulating, separating layer.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: March 20, 2018
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Neil H Talbot, Jordan M Neysmith, Dustin Tobey
  • Patent number: 9853019
    Abstract: A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: December 26, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, David A. Kidd, Augustine Kuo
  • Patent number: 9852805
    Abstract: A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: December 26, 2017
    Assignee: Kilopass Technology, Inc.
    Inventors: Harry Luan, Tao Su, Steve Wang, Charlie Cheng
  • Patent number: 9786667
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9646970
    Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Peter L. D. Chang, Uygar E. Avci, David Kencke, Ibrahim Ban
  • Patent number: 9646690
    Abstract: A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 9, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Wataru Otsuka, Jun Sumino, Tomohito Tsushima, Makoto Kitagawa, Takafumi Kunihiro
  • Patent number: 9496016
    Abstract: A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: November 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Jae Lee, Kyoung-Mok Son, Sang-Gi Ko, Si-Woo Kim
  • Patent number: 9436845
    Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Sami Rosenblatt
  • Patent number: 9041090
    Abstract: Methods for forming a string of memory cells and apparatuses having a vertical string of memory cells are disclosed. One such string of memory cells can be formed at least partially in a stack of materials comprising a plurality of alternating levels of control gate material and insulator material. A memory cell of the string can include floating gate material adjacent to a level of control gate material of the levels of control gate material. The memory cell can also include tunnel dielectric material adjacent to the floating gate material. The level of control gate material and the tunnel dielectric material are adjacent opposing surfaces of the floating gate material. The memory cell can include metal along an interface between the tunnel dielectric material and the floating gate material. The memory cell can further include a semiconductor material adjacent to the tunnel dielectric material.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: May 26, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Akira Goda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 9012320
    Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaegoo Lee, Kil-Su Jeong, Hansoo Kim, Youngwoo Park
  • Patent number: 9000409
    Abstract: The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 7, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Ming Liu
  • Patent number: 8956940
    Abstract: An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. Source and body regions inside the active region are at source potential and source and body regions outside the isolation trench are at drain potential. The device can be made using a three-mask or four-mask process.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 17, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 8896123
    Abstract: Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaehun Jeong, Hansoo Kim, Jaehoon Jang, Hoosung Cho, Kyoung-Hoon Kim
  • Patent number: 8896070
    Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Seagate Technology LLC
    Inventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
  • Patent number: 8890214
    Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Nan Ya Technology Corporation
    Inventors: Panda Durga, Jaydip Guha, Robert Kerr
  • Patent number: 8871590
    Abstract: A thin film transistor array substrate includes a substrate, a gate line and a data line arranged to cross each other and to define a pixel region on the substrate, a first common line disposed to be parallel to the gate line and to cross the data line, a switch element disposed at an intersection of the gate line and data line, a first pixel electrode formed to overlap the first common line, and a second pixel electrode branched from the first pixel electrode in a plurality of strips, a second common line opposite to the first common line in the center of the pixel region, a second common electrode branched from the second common line toward the pixel region into a plurality of strips, and a third common electrode branched to overlap the data line from the second common line, and a first storage electrode branched from the first common line into the pixel region, and a second storage electrode extended to overlap the first storage electrode from the first pixel electrode.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 28, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jun Ho Choi, Heung Lyul Cho
  • Patent number: 8860142
    Abstract: A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Debora Chyiu Hyia Poon, Alex K H See, Francis Benistant, Benjamin Colombeau, Yun Ling Tan, Mei Sheng Zhou, Liang Choo Hsia
  • Patent number: 8853028
    Abstract: A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged on a protective film in the pixel region, a second common electrode overlapping the data line, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film and the organic insulation film, and has inclined surfaces connected to the protective film within the pixel region.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: October 7, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jin Hee Jang, Heung Lyul Cho
  • Patent number: 8823136
    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Wayne H. Woods
  • Patent number: 8796778
    Abstract: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 8728903
    Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Junichi Shiozawa
  • Patent number: 8722498
    Abstract: Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Andy Wei
  • Publication number: 20140092506
    Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: AKM AHSAN, Walid M. HAFEZ
  • Publication number: 20140078832
    Abstract: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: EON SILICON SOLUTION, INC.
    Inventors: TAKAO AKAOGI, YIDER WU, YI-HSIU CHEN, HUNG-HUI LAI
  • Publication number: 20140054718
    Abstract: An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kamal M. Karda, Shyam Surthi, Wolfgang Mueller, Sanh D. Tang
  • Patent number: 8629542
    Abstract: A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 ?m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: January 14, 2014
    Inventor: Glenn J. Leedy
  • Patent number: 8618602
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 31, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kiyonori Oyu
  • Patent number: 8618607
    Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, David Doman, Marc Tarabbia, Irene Lin, Jeff Kim, Chinh Nguyen, Steve Soss, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
  • Publication number: 20130328117
    Abstract: A solid-state non-volatile memory (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.
    Type: Application
    Filed: June 9, 2012
    Publication date: December 12, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Mads HOMMELGAARD, Andrew HORCH, Martin NISET
  • Patent number: 8598646
    Abstract: An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: December 3, 2013
    Assignee: Spansion LLC
    Inventors: Chun Chen, Shenqing Fang
  • Publication number: 20130313653
    Abstract: A field effect transistor is described. In accordance with the one example, the transistor includes a semiconductor substrate, a gate pad for receiving a gate signal, a number of transistor cells integrated in the substrate, wherein each transistor cell has at least one gate electrode. The transistor further includes a number of gate runners for distributing the gate signal to the gate electrodes of the transistor cells. Each individual gate runner is electrically coupled to the gate pad via a respective gate resistor having a defined resistance.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Helmut Brech
  • Publication number: 20130313615
    Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiann-Tyng TZENG, Chih-Liang CHEN, Yi-Feng CHEN, Kam-Tou SIO, Shang-Chih HSIEH, Helen Shu-Hui CHANG
  • Patent number: 8592898
    Abstract: A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Publication number: 20130307054
    Abstract: One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.
    Type: Application
    Filed: September 7, 2012
    Publication date: November 21, 2013
    Inventors: Shinichi YASUDA, Kosuke Tatsumura, Mari Matsumoto, Koichiro Zaitsu, Masato Oda, Atsuhiro Kinoshita, Daisuke Hagishima, Yoshifumi Nishi, Takahiro Kurita, Shinobu Fujita
  • Publication number: 20130285063
    Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer on a substrate, which is patterned by a multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer, which is patterned by a first mask to remain the gate insulation layer on the gate; depositing a semiconductor layer, which is patterned by a second mask to remain the semiconductor layer on the gate; and depositing a second metal layer, which is patterned by a third mask to form a source and a drain.
    Type: Application
    Filed: May 9, 2012
    Publication date: October 31, 2013
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hua Huang, Pei Jia
  • Publication number: 20130277726
    Abstract: A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.
    Type: Application
    Filed: August 29, 2012
    Publication date: October 24, 2013
    Inventor: Sang Hyuk NAM