Cmos Gate Array (epo) Patents (Class 257/E27.108)
  • Patent number: 10678977
    Abstract: A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mao-Wei Chiu, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Chi-Yu Lu
  • Patent number: 10552567
    Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 4, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Deniz E. Civay, Elise Laffosse
  • Patent number: 10546089
    Abstract: Fabrication of a circuit board is facilitated by automatically determining an optimized power plane shape for a power plane of the circuit board, including ascertaining for the power plane a source location(s) and a sink location(s), where the source supplies power to the sink across the power plane. A center of current density is determined for the power plane shape, and a respective power plane sub-shape is incrementally generated between the center of current density and each source and sink location to, in part, supply a desired operational voltage from the source location(s) to the sink location(s) across the power plane. The respective power plane sub-shapes are combined into the optimized power plane shape. Further, the process includes initiating fabricating of the circuit board using, at least in part, the optimized power plane shape to provide the power plane shape within the circuit board.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matteo Cocchini, Edward N. Cohen, Nicholas G. Danyluk, Zachary T. Dreiss, John S. Werner
  • Patent number: 10521229
    Abstract: A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 31, 2019
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Chao-Hung Chang, Avidan Akerib
  • Patent number: 10224336
    Abstract: Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David Daycock
  • Patent number: 9985040
    Abstract: Integrated circuitry has an array circuitry region having a repeating array of electronic components. An adjacent circuitry region is immediately laterally adjacent to and contacts one elongated major peripheral side of the array circuitry region. The adjacent circuitry region is distinct in structure from the array circuitry region where contacting the array circuitry region and distinct in operation from the array circuitry region. The array circuitry region and the adjacent circuitry region have a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the array circuitry region. Other embodiments are disclosed.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: David Daycock
  • Patent number: 9436795
    Abstract: A method of verifying a layout of a semiconductor integrated circuit is disclosed. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process of the semiconductor integrated circuit, executing layout correction with respect to the first layout information, comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires of the semiconductor integrated circuit before and after the execution of the layout correction, and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: September 6, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Mitsuru Onodera
  • Patent number: 9412757
    Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 9, 2016
    Assignee: SOCIONEXT INC.
    Inventor: Masaki Tamaru
  • Patent number: 9041068
    Abstract: A 3D semiconductor device and a 3D logic array structure thereof are provided. The 3D semiconductor device includes an array structure, a periphery line structure and a 3D logic array structure. The array structure has Y contacts located at a side of the array structure. Y is within MN-1 to MN. Y, M and N are natural numbers. M is larger or equal to 2. The 3D logic array structure includes N sets of gate electrodes, an input electrode and Y output electrodes. Each set of the gate electrodes has M gate electrodes. The Y output electrodes connect the Y contacts. The M·N gate electrodes and the input electrode connect the periphery line structure.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Hung Chen
  • Patent number: 9035360
    Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Patent number: 8987120
    Abstract: The present invention relates to a flat panel display device comprising a polysilicon thin film transistor and a method of manufacturing the same. Grain sizes of polysilicon grains formed in active channel regions of thin film transistors of a driving circuit portion and a pixel portion of the flat panel display device are different from each other. Further, the flat panel display device comprising P-type and N-type thin film transistors having different particle shapes from each other.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Yong Park, Jae-Bon Koo, Hye-Hyang Park, Ki-Yong Lee, Ul-Ho Lee
  • Patent number: 8952425
    Abstract: An integrated circuit includes at least four linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other and each respectively including a gate electrode portion and an extending portion that extends away from the gate electrode portion. The gate electrode portions of the linear-shaped conductive structures respectively form gate electrodes of different transistors, such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of a first transistor type and does not form a gate electrode of any transistor of a second transistor type, and such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of the second transistor type and does not form a gate electrode of any transistor of the first transistor type. Extending portions of the at least four linear-shaped conductive structures include at least two different extending portion lengths.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 10, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8952424
    Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Cambridge Silicon Radio Ltd
    Inventor: Rainer Herberholz
  • Patent number: 8946781
    Abstract: An integrated circuit includes four parallel positioned linear-shaped structures each including a gate electrode portion and an extension portion. Gate electrode portions of two of the four linear-shaped structures respectively form gate electrodes of first and second transistors of a first transistor type. Gate electrode portions of two of the four linear-shaped structures respectively form a gate electrodes of first and second transistors of a second transistor type. Four contacting structures are respectively connected to the extension portions of the four linear-shaped structures such that each extension portion has a respective contact-to-end distance. At least two of the contact-to-end distances are different. A fifth linear-shaped structure forms gate electrodes of transistors respectively positioned next to the first transistors of the first and second transistor types.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 3, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8928092
    Abstract: A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hauk Han, Yong-Il Kwon, JungSuk Oh, Tae sun Ryu, Jeonggil Lee
  • Patent number: 8921177
    Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8921896
    Abstract: A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 30, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8921897
    Abstract: A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8901704
    Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8884338
    Abstract: A semiconductor integrated-circuit device is disclosed. The semiconductor integrated-circuit device uses a filter, which includes a standard capacitor, as a standard cell connecting a memory cell with a logic cell. As such, the semiconductor integrated-circuit device can minimize a glitch phenomenon of power/ground voltages and provide stability of power/ground voltages.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: November 11, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: Ki Joong Kim
  • Patent number: 8884337
    Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 8841774
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • Patent number: 8836040
    Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati, Animesh Datta
  • Patent number: 8823062
    Abstract: A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 2, 2014
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8803237
    Abstract: A distance “a” from a first gate electrode of a first transistor of a high-frequency circuit to a first contact is greater than a distance “b” from a second electrode of a second transistor of a digital circuit to a second contact. The first contact is connected to a drain or source of the first transistor, and the second contact is connected to a drain or source of the second transistor.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takafumi Kuramoto, Yasutaka Nakashiba
  • Patent number: 8803202
    Abstract: A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Jen-Bin Hsu, Chung Long Cheng, Mong-Song Liang
  • Patent number: 8803204
    Abstract: In a manufacturing method of a solid-state image pickup device according to an embodiment, a transfer gate electrode is formed in a predetermined position on an upper surface of a first conductive semiconductor area, through a gate insulating film. A second conductive charge storage area is formed in an area adjacent to the transfer gate electrode in the first conductive semiconductor area. A sidewall is formed on a side surface of the transfer gate electrode. An insulating film is formed to extend from a circumference surface of the sidewall on a side of the charge storage area to a position partially covering the upper part of the charge storage area. A first conductive charge storage layer is formed in the charge storage area by implanting first conductive impurities from above, into the charge storage area which is partially covered with the insulating film.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: August 12, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Ohta, Hitohisa Ono
  • Patent number: 8796793
    Abstract: A magnetoresistive element includes: a lower magnetic layer; a barrier layer; and an upper magnetic layer. The barrier layer is provided on the lower magnetic layer. The upper magnetic layer is provided on the barrier layer. One of magnetization directions of the lower magnetic layer and the upper magnetic layer is fixed. The barrier layer has a first surface which includes a surface contacted with an upper surface of the lower magnetic layer. The upper magnetic layer has a second surface which includes a surface contacted with an upper surface of the barrier layer. Each of the first surface and the second surface is larger than the upper surface of the lower magnetic layer in area.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 5, 2014
    Assignees: Renesas Electronics Corporation, NEC Corporation
    Inventors: Yasuaki Ozaki, Hiroaki Honjyou
  • Patent number: 8759163
    Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: June 24, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Wen-Shen Chou, Jui-Cheng Huang
  • Patent number: 8729639
    Abstract: According to one embodiment, a semiconductor device includes a gate electrode formed on a substrate with a gate insulation film interposed therebetween, and a source region of a first conductivity type and a drain region of a second conductivity type reverse to the first conductivity type, which are formed so as to hold the gate electrode therebetween within the substrate. The work function of a first region on the source region side within the gate electrode is shifted toward the first conductivity type as compared to the work function of a second region on the drain region side within the gate electrode.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakazu Goto
  • Patent number: 8704311
    Abstract: The semiconductor device includes a first transistor including a first impurity layer of a first conductivity type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, and a first gate electrode formed above the first gate insulating film, and a second transistor including a second impurity layer of the second conductivity type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and having a thickness different from that of the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer and having a film thickness equal to that of the first gate insulating film and a second gate electrode formed above the second gate insulating film.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazushi Fujita, Taiji Ema, Hiroyuki Ogawa
  • Patent number: 8658489
    Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 25, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8604557
    Abstract: A semiconductor memory device includes: a first n-type transistor; a first p-type transistor; a first wiring layer having a first interconnecting portion for connecting a drain of the first n-type transistor and a drain of the first p-type transistor; and a second wiring layer having a first conductive portion electrically connected to the first interconnecting portion.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Narumi Ohkawa
  • Patent number: 8592907
    Abstract: It is an object to achieve high performance of a semiconductor integrated circuit depending on not only a microfabrication technique but also another way and to achieve low power consumption of a semiconductor integrated circuit. A semiconductor device is provided in which a crystal orientation or a crystal axis of a single-crystalline semiconductor layer for a MISFET having a first conductivity type is different from that of a single-crystalline semiconductor layer for a MISFET having a second conductivity type. A crystal orientation or a crystal axis is such that mobility of carriers traveling in a channel length direction is increased in each MISFET. With such a structure, mobility of carriers flowing in a channel of a MISFET is increased, and a semiconductor integrated circuit can be operated at higher speed. Further, low voltage driving becomes possible, and low power consumption can be achieved.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 8592922
    Abstract: A transistor device is provided that includes a substrate, a first channel region formed in a first portion of the substrate and being doped with a dopant of a first type of conductivity, a second channel region formed in a second portion of the substrate and being doped with a dopant of a second type of conductivity, a gate insulating layer formed on the first channel region and on the second channel region, a dielectric capping layer formed on the gate insulating layer, a first gate region formed on the dielectric capping layer over the first channel region, and a second gate region formed on the dielectric capping layer over the second channel region, wherein the first gate region and the second gate region are made of the same material, and wherein one of the first gate region and the second gate region comprises an ion implantation.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jacob C. Hooker, Markus Mueller
  • Patent number: 8575761
    Abstract: An array of functional cells includes a subset of cells powered by at least one supply rail. That supply rail is formed of first segments located on a first metallization level and second segments located on a second metallization level with at least one conductor element extending between the first and second segments to electrically connect successive segments of the supply rail.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.A.
    Inventor: Remy Chevallier
  • Patent number: 8536654
    Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: September 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • Patent number: 8530288
    Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 8524566
    Abstract: Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 3, 2013
    Assignee: GlobalFoundries, Inc.
    Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
  • Patent number: 8519444
    Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
  • Patent number: 8513707
    Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Cambridge Silicon Radio Ltd.
    Inventor: Rainer Herberholz
  • Patent number: 8476706
    Abstract: A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: July 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Brian J. Greene, Yue Liang, Xiaojun Yu
  • Patent number: 8466496
    Abstract: A complementary metal oxide semiconductor (CMOS) device that may include a substrate having a first active region and a second active region that are separated from one another by an isolation region. An n-type semiconductor device is present on the first active region that includes a first gate structure having a first gate dielectric layer and an n-type work function metal layer, wherein the n-type work function layer does not extend onto the isolation region. A p-type semiconductor device is present on the second active region that includes a second gate structure having a second gate dielectric layer and a p-type work function metal layer, wherein the p-type work function layer does not extend onto the isolation region. A connecting gate structure extends across the isolation region into direct contact with the first gate structure and the second gate structure.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Xiaojun Yu, Dureseti Chidambarrao, Brian J. Greene, Yue Liang
  • Patent number: 8460996
    Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
  • Patent number: 8456883
    Abstract: CMOS devices are provided in a substrate having a topmost metal layer comprising metal landing pads and metal connecting pads. A plurality of magnetic tunnel junction (MTJ) structures are provided over the CMOS devices and connected to the metal landing pads. The MTJ structures are covered with a dielectric layer that is polished until the MTJ structures are exposed. Openings are etched in the dielectric layer to the metal connecting pads. A seed layer is deposited over the dielectric layer and on inside walls and bottom of the openings. A copper layer is plated on the seed layer until the copper layer fills the openings. The copper layer is etched back and the seed layer is removed. Thereafter, an aluminum layer is deposited over the dielectric layer, contacting both the copper layer and the MTJ structures, and patterned to form a bit line.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: June 4, 2013
    Assignee: Headway Technologies, Inc.
    Inventor: Daniel Liu
  • Patent number: 8445943
    Abstract: A semiconductor integrated circuit device includes: a plurality of data holding circuits; and a plurality of wells. The plurality of data holding circuits is provided in a substrate of a first conductive type. Each of the plurality of data holding circuits includes a first well of the first conductive type and a second well of a second conductive type different from the first conductive type. The plurality of wells is arranged in two directions for the each of the plurality of data holding circuits.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Patent number: 8426978
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • Patent number: 8421159
    Abstract: In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8410555
    Abstract: There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: April 2, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Wenwu Wang, Huilong Zhu, Shijie Chen, Dapeng Chen