Input And Output Buffer/driver (epo) Patents (Class 257/E27.11)
  • Patent number: 9859892
    Abstract: A semiconductor apparatus may include a transmission circuit, a reception circuit, and a pad commonly coupled to the transmission circuit and the reception circuit. When either the transmission circuit or the reception circuit is activated, parasitic capacitance of a line coupled to the transmission circuit, the reception circuit, and the pad is varied.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SK hynix Inc.
    Inventor: Sun Ki Cho
  • Patent number: 9673800
    Abstract: An analog switch circuit is disclosed. The analog switch circuit includes a MOSFET and a control switch. The MOSFET includes a drain electrode, a source electrode, a gate electrode, and a body electrode. A gate bias is applied on the gate electrode to control whether the MOSFET is ON or OFF. The control switch includes a control terminal, a first terminal, a second terminal, and a third terminal. A control bias relating to the gate bias is applied to the control terminal so that the first terminal is connected to the second terminal when the MOSFET is ON, and the first terminal is connected to the third terminal when the MOSFET is OFF. The second terminal is connected to a first voltage source providing a first bias. The third terminal is connected to a second voltage source providing a second bias different from the first bias.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: June 6, 2017
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Guan-Yu Chen, Leaf Chen
  • Patent number: 9647664
    Abstract: A semiconductor apparatus may include an output driver configured to output an internal signal to an external device. The output driver may include a pad coupled to the external device, a pull-up driver coupled to the pad at an end thereof, a first resistance element coupled to the pull-up driver at an end thereof, and configured to receive a first source voltage at the other end thereof, a pull-down driver coupled to the pad at an end thereof, and a second resistance element coupled to the pull-down driver at an end thereof, and configured to receive a first ground voltage at the other end thereof.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 9, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyun Bae Lee
  • Patent number: 9601921
    Abstract: Embodiments relate to electrostatic discharge (ESD) protection. One embodiment includes a tie-off circuit including a multiple field effect transistors (FETs), a first internal node, a second internal node, a first output node and a second output node. A node isolation circuit is connected to the first output node and the second output node of the tie-off circuit. The node isolation circuit includes a first FET with a third output node and a second FET with a fourth output node. The third output node and the fourth output node are electrically isolated from the first internal node and the second internal node.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Chen Guo, Yutaka Nakamura, Jun Sawada
  • Patent number: 9589893
    Abstract: A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masafumi Tomoda, Masayuki Tsukuda
  • Patent number: 9557755
    Abstract: An interface pad circuit configured for conveying an electrical signal from a semiconductor chip component to a component external to the semiconductor chip component, the interface pad circuit includes: a control circuit; a plurality of semiconductor elements, the semiconductor elements having respective bulk terminals and being controlled by the control circuit; and a connection pad; wherein at least two of the semiconductor elements are configured for providing a plurality of non-zero logic voltage levels to the connection pad; and wherein the control circuit is configured to apply a voltage level to the bulk terminals of the at least two of the semiconductor elements providing the non-zero logic voltage levels, the voltage level applied by the control circuit corresponding to the highest voltage level of the plurality of non-zero logic voltage levels.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 31, 2017
    Assignee: GN RESOUND A/S
    Inventor: Henrik Ahrendt
  • Patent number: 9391618
    Abstract: A high-voltage fail-safe input/output (I/O) interface circuit includes a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit, and a selector circuit configured to couple, to a power supply line of the I/O interface circuit one of an output of the voltage-divider circuit or and I/O supply voltage. The voltage-divider circuit and the selector circuit are implemented on the same chip with the I/O interface circuit.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: July 12, 2016
    Assignee: Broadcom Corporation
    Inventor: Darrin Robert Benzer
  • Patent number: 9252166
    Abstract: The present invention discloses a capacitor for a TFT array substrate and a method of manufacturing the same, and the present invention further discloses a shift register, a gate driver, an array substrate and a display device using the capacitor. The TFT array substrate comprises a TFT gate layer, a gate insulation layer, a first ITO layer, a TFT active layer, a TFT source-drain layer, a passivation layer and a second ITO layer formed sequentially on a glass substrate, and the capacitor is consisted of the first ITO layer, the passivation layer and the second ITO layer. In addition, the second ITO layer is connected with the TFT gate layer in a region where the capacitor is located, thereby forming two capacitors connected in parallel; or, the first ITO layer is connected with the TFT gate layer in the region where the capacitor is located, thereby also forming two capacitors connected in parallel.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 2, 2016
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xiaohe Li, Xianjie Shao
  • Patent number: 9019255
    Abstract: An organic light emitting display apparatus includes a polarizer film arranged on a substrate or an encapsulation substrate that faces an image realized by a display unit, wherein the polarizer film includes a plurality of regions having different light transmittances. By using the polarizer film, a luminance difference due to a voltage drop may be compensated for so that a uniform luminance may be obtained when the image is realized.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: April 28, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Joo Hwang, Hee-Chul Jeon, Jung-I Yun, Sae-Hee Lim
  • Patent number: 8975632
    Abstract: Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Yoshifumi Tanada, Mitsuaki Osame, Aya Anzai, Ryota Fukumoto
  • Patent number: 8941185
    Abstract: An active matrix substrate of the present invention includes: a first signal line and a second signal line which are aligned in a column direction in which the first signal line and the second signal line extend; a first transistor and a second transistor; and a first electrode and a second electrode, the first signal line being connected via the first transistor to the first electrode, and the second signal line being connected via the second transistor to the second electrode, and the first signal line having a first end which is one of both ends of the first signal line and faces the second signal line, the first end including a tapered part which is tapered toward the second signal line. This makes it possible to prevent a leakage defect from occurring between two signal lines which are aligned in a direction in which the two signal lines extend.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: January 27, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Kazuyori Mitsumoto
  • Patent number: 8884337
    Abstract: An output buffer includes an input/output end, a voltage source, a first transistor and a second transistor. The first transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The second transistor includes a first end coupled to the input/output end, a second end coupled to the voltage source, and a control end coupled to the voltage source. The control end of the first transistor and the control end of the second transistor are substantially perpendicular to each other, and the punch through voltage of the first transistor is higher than the punch through voltage of the second transistor.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Tzu Wang, Ping-Chen Chang, Tien-Hao Tang
  • Publication number: 20140246702
    Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
    Type: Application
    Filed: September 26, 2012
    Publication date: September 4, 2014
    Applicant: BAYSAND INC.
    Inventor: Baysand Inc.
  • Publication number: 20140246701
    Abstract: Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.
    Type: Application
    Filed: September 26, 2012
    Publication date: September 4, 2014
    Applicant: BAYSAND INC.
    Inventor: Baysand Inc.
  • Patent number: 8710545
    Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 29, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Da-Wei Lai, Handoko Linewih
  • Patent number: 8664725
    Abstract: A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: March 4, 2014
    Assignee: Altera Corporation
    Inventors: Girish Venkitachalam, Che Ta Hsu, Fangyun Richter, Peter J. McElheny
  • Patent number: 8507946
    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 13, 2013
    Assignees: Vanguard International Semiconductor Corporation, National Chiao Tung University
    Inventors: Yeh-Jen Huang, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
  • Patent number: 8501622
    Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 6, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ker-Min Chen
  • Patent number: 8441135
    Abstract: A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 14, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hideyuki Yoko, Kayoko Shibata
  • Patent number: 8390031
    Abstract: Provided is a pad layout structure of a semiconductor chip capable of preventing lead-broken problems when packaging the semiconductor chip with a high aspect ratio in a tape carrier package (TCP). In the pad layout structure of the semiconductor chip, a plurality pads are arranged along upper, lower, left and right sides of the semiconductor chip with a high aspect ratio, and a longitudinal width of pads arranged at the left and right sides and a transverse width of pads arranged at both edges of the upper and lower sides are greater than a transverse width of pads arranged at centers of the upper and lower sides.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 5, 2013
    Assignee: Silicon Works Co., Ltd.
    Inventors: Dae-Keun Han, Dae-Seong Kim, Joon-Ho Na
  • Patent number: 8354722
    Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: John B. Campi, Jr., Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Rahul Mishra, Mujahid Muhammad
  • Patent number: 8334538
    Abstract: A thin film transistor array panel includes: an insulation substrate; a gate line disposed on the insulation substrate and including a compensation pattern protruding from the gate line; a first data line and a second data line both intersecting the gate line; a first thin film transistor connected to the gate line and the first data line; a second thin film transistor connected to the gate line and the second data line; and a first pixel electrode and a second pixel electrode connected to the first thin film transistor and the second thin film transistor, respectively. The first pixel electrode and the second pixel electrode share the compensation pattern.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: December 18, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ho-Jun Lee, Yeo-Geon Yoon, Hyoung-Wook Lee, Mi-Ae Lee
  • Publication number: 20120292667
    Abstract: Embodiments provide crossbar structures, and reconfigurable circuits that contain crossbar structures, that include n inputs and an output, where n is an integer, chains of transistors coupled to the n inputs and the output, a plurality of control signal elements—each coupled to one or more transistors of the plurality of chains of transistors to selectively couple said n inputs to the output—and an additional chain of transistors coupled to at least some of the plurality of control signal elements and the output to selectively couple a constant output voltage to the output. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: August 2, 2012
    Publication date: November 22, 2012
    Inventors: Olivier V. Lepape, Philippe Piquet
  • Patent number: 8304813
    Abstract: A connection between a first circuit within an I/O region of an integrated circuit chip and a second circuit within a core region of the chip. The first circuit is connected to a bonding pad through a first conductor in a first layer of an I/O region. The second circuit is connected to the bonding pad through a second conductor in a second layer of an I/O region above the first layer.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: November 6, 2012
    Assignee: SanDisk Technologies, Inc.
    Inventors: Paul Lassa, Paul Paternoster, Brian Cheung
  • Patent number: 8283698
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting an integrated circuit (IC) having a first voltage potential, a first power supply potential and a second power supply potential. The ESD circuit includes a first NPN bipolar transistor having a first N-doped junction, a second N-doped junction and a third P-doped base junction. The first N-doped junction is coupled to the first voltage potential and the second N-doped junction is coupled to the first power supply potential. The ESD circuit also includes a first PNP bipolar transistor having a first P-doped junction, a second P-doped junction and a third N-doped base junction. The first P-doped junction is coupled to the first voltage potential and the second P-doped junction is coupled to the second power supply potential. The third P-doped base junction of the first NPN bipolar transistor is coupled to the third N-doped base junction of the first PNP bipolar transistor.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 9, 2012
    Assignee: Sofics BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp
  • Patent number: 8242613
    Abstract: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Chetan Verma, Shailesh Kumar, Meng Kong Lye
  • Patent number: 8154054
    Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 10, 2012
    Assignee: Panasonic Corporation
    Inventor: Masato Maede
  • Patent number: 8138500
    Abstract: In a pixel portion, a scan signal line and an auxiliary capacitor line are formed using a second conductive film, and a data signal line is formed using a first conductive film. In a TFT portion, a gate electrode is formed using the first conductive film and electrically connected to the scan signal line formed using the second conductive film through an opening in a gate insulating film. Further, a source electrode and a drain electrode are formed using the second conductive film. In the auxiliary capacitor portion, the auxiliary capacitor line formed using the second conductive film serves as a lower electrode, the pixel electrode serves as an upper electrode, and the passivation film used as a dielectric film is interposed between the capacitor electrodes.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kunio Hosoya
  • Patent number: 8071407
    Abstract: An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: December 6, 2011
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Lung Fang, Hsiang-Lin Lin, Han-Tu Lin
  • Patent number: 8067277
    Abstract: An active matrix pixel device is provided, for example an electroluminescent display device, the device comprising circuitry supported by a substrate and including a polysilicon TFT (10) and an amorphous silicon thin film PIN diode (12). Polysilicon islands are formed before an amorphous silicon layer is deposited for the PIN diode. This avoids the exposure of the amorphous silicon to high temperature processing. The TFT comprises doped source/drain regions (16a,17a), one of which (17a) may also provide the n-type or p-type doped region for the diode. Advantageously, the requirement to provide a separate doped region for the photodiode is removed, thereby saving processing costs. A second TFT (10b) having a doped source/drain region (16b,17b) of the opposite conductivity type may provide the other doped region (16b) for the diode, wherein the intrinsic region (25) is disposed laterally between the two TFTs, overlying each of the respective polysilicon islands.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: November 29, 2011
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Steven C. Deane
  • Publication number: 20110193086
    Abstract: A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
    Type: Application
    Filed: September 27, 2010
    Publication date: August 11, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Cheol LEE, Chi-Sung OH, Jin-Kuk KIM
  • Patent number: 7977762
    Abstract: An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 12, 2011
    Assignee: Alvand Technologies, Inc.
    Inventors: Mansour Keramat, Mehrdad Heshami, Syed S. Islam
  • Patent number: 7965273
    Abstract: The present invention provides a buffer and an organic light emitting display that employs the buffer. The buffer is installed in a scan driver or a data driver, which generates scan signals and data signals, respectively, to drive the organic light emitting display. The buffer of the present invention is configured of p-channel metal-oxide-semiconductor (PMOS) transistors, and therefore the scan driver or data driver that includes the buffer can be mounted on a display panel. Various arrangements of the PMOS transistors are proposed for the buffer of the present invention. The buffer of the present invention effectively prevents leakage current that could be generated in the circuit of the buffer.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: June 21, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Wang-jo Lee, Do-youb Kim
  • Patent number: 7935967
    Abstract: The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid crystal display device, line resistance is decreased.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: May 3, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Shunpei Yamazaki
  • Publication number: 20110089470
    Abstract: In a semiconductor device, a plurality of interface cells is disposed on four sides of an LSI chip in connection with a logic circuit area including a plurality of logic cells. Each interface cell may include four functional blocks which are vertically or horizontally aligned without being rotated, thus forming an I/O buffer. The left I/O buffer has a vertical layout in which functional blocks are vertically aligned, whilst the upper I/O buffer has a horizontal layout in which functional blocks are horizontally aligned. This makes it possible to fix the same length direction of gates of transistors with respect to both the functional blocks of I/O buffers and the logic cells, so that engineers do not need to consider characteristic variations of transistors due to positional differences of transistors when designing the circuitry of an LSI chip.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 21, 2011
    Inventor: MUTSUMI AOKI
  • Publication number: 20110084404
    Abstract: One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit.
    Type: Application
    Filed: October 7, 2010
    Publication date: April 14, 2011
    Applicant: Elpida Memory, Inc.
    Inventors: Hideyuki Yoko, Kayoko Shibata
  • Patent number: 7923726
    Abstract: Disclosed is a TFT substrate for a display apparatus comprising a gate wiring including a gate electrode, a data wiring including a data line, a source electrode connected to the data line, and a drain electrode connected to a pixel electrode, and a semiconductor layer disposed between the gate wiring and the data wiring, wherein the semiconductor layer under the drain electrode is disposed within an area overlapping the gate electrode and the semiconductor layer under the source electrode extends outward to an area not overlapping the gate electrode. Advantageously, the present disclosure provides a TFT substrate for a display apparatus having a high aperture ratio and causing less afterimaging, and a manufacturing method of the same.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-sun Na, Sang-ki Kwak, Dong-gyu Kim, Kyung-phil Lee
  • Patent number: 7897999
    Abstract: A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Furuta
  • Patent number: 7863687
    Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Sai
  • Publication number: 20100327324
    Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.
    Type: Application
    Filed: August 31, 2010
    Publication date: December 30, 2010
    Applicant: PANASONIC CORPORATION
    Inventor: Masato Maede
  • Patent number: 7816708
    Abstract: In a semiconductor chip in which external connection pads are arranged in three or more rows in a staggered configuration at the peripheral portion thereof, a first pad which is arranged in the outermost row is used as a power supply pad or a ground pad for an internal core circuit. To the first pad, a second pad which is arranged in the second outermost row is connected with a metal in the same layer as a pad metal. The resistance of a power supply line to the internal core circuit has a value of the parallel resistance of a resistance from the first pad and a resistance from the second pad, which is by far lower than the resistance from the first pad. Therefore, it is possible to prevent circuit misoperation resulting from an IR drop in the power supply of the internal core circuit.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventor: Masato Maede
  • Patent number: 7795734
    Abstract: To provide a semiconductor device composed of a semiconductor element or a group of semiconductor elements, in which a crystalline semiconductor film having as few grain boundaries as possible in a channel formation region is formed on an insulating surface, which can operate at high speed, which have high current drive performance, and which are less fluctuated between elements.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: September 14, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi
  • Publication number: 20100214513
    Abstract: A high contrast display having a first substrate, a transistor array substrate and a light shielding layer is provided, wherein the first substrate includes a common electrode. The transistor array substrate includes a plurality of pixels arranged in array, wherein each pixel includes a transistor and a pixel electrode electrically connected thereto. The light shielding layer is disposed between the first substrate and the transistor array substrate. The high contrast display is able to protect the transistors from producing current leakage, so as to improve display quality.
    Type: Application
    Filed: November 24, 2009
    Publication date: August 26, 2010
    Applicant: WINTEK CORPORATION
    Inventors: Hen-Ta Kang, Wen-Chun Wang
  • Patent number: 7714362
    Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: May 11, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ker-Min Chen
  • Patent number: 7656004
    Abstract: A display device includes a display panel, first and second gate drivers and a data driver. The display panel includes pixel regions respectively having first, second and third pixels. The first pixel is coupled to first, second gate lines and a data line. The second gate line is adjacent to the first gate line. The second pixel is coupled to the first gate line and a first data line. The third pixel is coupled to the first gate line and a second data line. The first gate driver provides the first gate line with a first gate driving signal, and the second gate driver provides the second gate line with a second gate driving signal. The data driver provides first and second data lines with image signal. The display quality of the display device may be enhanced and the number of the data lines may be reduced.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Jeon, Hyung-Guel Kim
  • Patent number: 7655979
    Abstract: There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: February 2, 2010
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Chang-Ki Jeon, Sung-Iyong Kim, Tae-hun Kwon
  • Publication number: 20100017775
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: September 24, 2009
    Publication date: January 21, 2010
    Inventors: Yusuke KANNO, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 7646023
    Abstract: A thin film transistor (TFT) array panel effectively minimizing light leakage current and a liquid crystal display including the same. The panel includes a transistor structure having a gate electrode formed on an insulating substrate; a semiconductor layer formed on and insulated from the gate electrode; a light blocking layer formed around and overlapping a portion of the gate electrode; a data line intersecting the gate line to form a source electrode, which overlaps a portion of the semiconductor layer; a drain electrode opposing to the source electrode and overlapping a portion of the semiconductor layer, and a pixel electrode formed on and insulated from the transistor structure and electrically connected to the drain electrode.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: January 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-han Park, Jin Jeon
  • Patent number: 7642710
    Abstract: A pixel structure electrically connected to a scan line, a data line and a power line is provided. The pixel structure includes a current control unit, a pixel electrode and a redundant active device. The current control unit is electrically connected to the scan line, the data line and the power line. The pixel electrode is electrically connected to the current control unit. The redundant active device is electrically connected to the pixel electrode and the current control unit, and the redundant active device is electrically insulated from the power line. Moreover, an organic electro-luminescence displaying unit and a repairing method thereof are further provided.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: January 5, 2010
    Assignee: Au Optronics Corporation
    Inventors: Chih-Wen Yao, Hsin-Hung Lee
  • Patent number: 7566923
    Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: July 28, 2009
    Assignee: LSI Corporation
    Inventors: Donald T. McGrath, Gregory Winn, Scott C. Savage