Including Insulator On Semiconductor, E.g. Soi (silicon On Insulator) (epo) Patents (Class 257/E27.112)
  • Patent number: 10756724
    Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Max Samuel Aubain, Clint Kemerling
  • Patent number: 10693445
    Abstract: Provided are integrated circuits that include one or more magnetic tunnel junction ring oscillator(s) with tunable frequency and methods for operating the same. Accordingly, an integrated circuit is provided that includes a ring oscillator. The ring oscillator includes an input voltage terminal, an output voltage terminal, and an odd number of at least three inverters disposed electrically in series with one another between the input voltage terminal and the output voltage terminal. Each of the at least three inverters includes an NMOS transistor and one or more magnetic tunnel junctions (MTJs) disposed electrically in series with the NMOS transistor. The NMOS transistor of each of the at least three inverters is selectively tunable with regard to either or both of its threshold voltage and its effective channel width.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bin Liu, Eng Huat Toh
  • Patent number: 10615081
    Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: April 7, 2020
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 9900001
    Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Max Samuel Aubain, Clint Kemerling
  • Patent number: 9837439
    Abstract: The present disclosure provides a semiconductor device structure including a substrate having a semiconductor-on-insulator (SOI) region and a hybrid region, wherein the SOI region and the hybrid region are separated by at least one isolation structure, the SOI region being formed by a semiconductor layer provided over a substrate material and a buried insulating material interposed between the semiconductor layer and the substrate material, a semiconductor device provided in the SOI region, the semiconductor device comprising a gate structure and source and drain regions formed adjacent to the gate structure, and a diode structure provided in the hybrid region, the diode structure comprising a well region doped with dopants of a first conductivity type and a well portion doped with dopants of a second conductivity type embedded into the well region in the hybrid region.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Juergen Faul
  • Patent number: 9812351
    Abstract: A method includes patterning a 1st mandrel cell into a 1st mandrel layer disposed above a dielectric layer of a semiconductor structure. The 1st mandrel cell has 1st mandrels, 1st mandrel spaces and a mandrel cell pitch. A 2nd mandrel cell is patterned into a 2nd mandrel layer disposed above the 1st mandrel layer. The 2nd mandrel cell has 2nd mandrels, 2nd mandrel spaces, and the mandrel cell pitch. The 1st and 2nd mandrel cells are utilized to form metal line cells into the dielectric layer. The metal line cells have metal lines, spaces between the metal lines and a line cell pitch. The line cell pitch is equal to the mandrel cell pitch when the metal lines of the metal line cells are an even number. The line cell pitch is equal to half the mandrel cell pitch when the metal lines of the metal line cells are an odd number.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: November 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas Vincent Licausi, Guillaume Bouche, Lars Wolfgang Liebmann
  • Patent number: 9768160
    Abstract: Disclosed is a semiconductor device, an electronic circuit, and a method. The semiconductor device includes a semiconductor body; at least one transistor cell including a source region, a drift region, a body region separating the source region from the drift region, and a drain region in the semiconductor body, and a gate electrode dielectrically insulated from the body region by a gate dielectric; a source node connected to the source region and the body region; a contact node spaced apart from the body region and the drain region and electrically connected to the drain region; and a rectifier element formed between the contact node and the source node.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler, Anton Mauder
  • Patent number: 9673055
    Abstract: A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: June 6, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Patent number: 9666577
    Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 30, 2017
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National De La Recherche Scientifique
    Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 9490247
    Abstract: An IGBT (50) includes a p+ collector region (3) and an n?? drift region (1), in which a first transistor (TR1) and a second transistor (TR2) are formed on the n?? drift region (1). In the n?? drift region (1), a p-type hole extraction region (14) is formed in contact with the second transistor (TR2). When the IGBT (50) is in an on-state, electrons and holes flow through the first transistor (TR1), but a current does not flow through the second transistor (TR2). On the other hand, when the IGBT (50) is switched from the on-state to an off-state, holes flow through the first transistor (TR1), and holes flow through the hole extraction region (14) and the second transistor (TR2).
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: November 8, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Yoshimoto, Akio Shima, Digh Hisamoto
  • Patent number: 9476927
    Abstract: A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 25, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Troy L. Graves-Abe, Chandrasekharan Kothandaraman, Conal E. Murray
  • Patent number: 9400353
    Abstract: A silicon-based photonic crystal includes a silicon substrate, a first dielectric with a grating structure formed therein, and a second dielectric with a higher index of refraction that covers at least a portion of the grating structure. The first dielectric can be formed on the silicon substrate, or a Fabry-Perot optical cavity can be formed between the silicon substrate and the first dielectric. An instrument can excite a fluorophore coupled to the photonic crystal by focusing collimated incident light that includes the fluorophore's excitation wavelength to a focal line on the surface of the photonic crystal such that the focal line is substantially parallel to the grating direction and can detect fluorescence radiation emitted by the fluorophore in response to the incident light. To provide for fluorescence enhancement, the excitation wavelength and/or emission wavelength of the fluorophore can couple to an optical resonance of the photonic crystal.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 26, 2016
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Brian T. Cunningham, Sherine George, Anusha Pokhriyal, Vikram Chaudhery, Meng Lu
  • Patent number: 9040981
    Abstract: Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9041108
    Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz
  • Patent number: 9029951
    Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama
  • Patent number: 9006828
    Abstract: A display device includes a first electrode, a second electrode, an organic light emitting layer, a first transistor, and a second transistor. The first transistor includes a first semiconductor layer, a first conductive unit, a second conductive unit, a first gate electrode, and a first gate insulating film. The second transistor includes a second semiconductor layer, a third conductive unit, a fourth conductive unit, a second gate electrode, and a second gate insulating film. An amount of hydrogen included in the first gate insulating film is larger than an amount of hydrogen included in the second gate insulating film.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuyoshi Saito, Tomomasa Ueda, Yuya Maeda, Kentaro Miura, Shintaro Nakano, Tatsunori Sakano, Hajime Yamaguchi
  • Patent number: 9006842
    Abstract: A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Gwan Sin Chang, Zhiqiang Wu, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 8999793
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 7, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 9000556
    Abstract: Structure and method for fabricating a barrier layer that separates an electromechanical device and a CMOS device on a substrate. An example structure includes a protective layer encapsulating the electromechanical device, where the barrier layer may withstand an etch process capable of removing the protective layer, but not the barrier layer. The substrate may be silicon-on-insulator or a multilayer wafer substrate. The electromechanical device may be a microelectromechanical system (MEMS) or a nanoelectromechanical system (NEMS).
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Sebastian U. Engelmann, Michael A. Guillorn
  • Patent number: 8994019
    Abstract: The invention is to provide a structure of a semiconductor device which achieves quick response and high-speed drive by improving on-state characteristics of a transistor, and to provide a highly reliable semiconductor device. In a transistor in which a semiconductor layer, a source and drain electrode layers, a gate insulating film, and a gate electrode are sequentially stacked, a non-single-crystal oxide semiconductor layer containing at least indium, a Group 3 element, zinc, and oxygen is used as the semiconductor layer. The Group 3 element functions as a stabilizer.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8969867
    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yutaka Okazaki
  • Patent number: 8969938
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination of which is accompanied with appropriate etch.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam Shahidi
  • Patent number: 8963228
    Abstract: A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Arvind Kumar
  • Patent number: 8957477
    Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh, Chen-Hua Yu
  • Patent number: 8952418
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 8952454
    Abstract: An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: February 10, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Shimizu, Junichi Yamashita, Takuichiro Shitomi
  • Patent number: 8928080
    Abstract: A back-bias region is disposed on a substrate. A buried insulating layer covers the substrate and the back-bias region. A body is formed on the buried insulating layer and partially overlaps the back-bias region. A drain is in contact with the body. A gate electrode covers top and lateral surfaces of the body.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Patent number: 8921188
    Abstract: One illustrative method disclosed herein includes forming a trench within an isolated region of a bulk semiconductor substrate, forming a region of an insulating material in the trench and forming a semiconductor material within the trench and above the upper surface of the region of insulating material. A substrate disclosed herein includes an isolated substrate region in a bulk semiconductor substrate, a region of an insulating material that is positioned within a trench defined in the isolated substrate region and a semiconductor material positioned within the trench and above the upper surface of the region of insulating material.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 30, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ram Asra
  • Patent number: 8916950
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Patent number: 8912624
    Abstract: A semiconductor device and a method for manufacturing thereof are provided. The method includes a step of forming a first insulating film containing silicon and oxygen as its composition over a single-crystal semiconductor substrate, a step of forming a second insulating film containing silicon and nitrogen as its composition over the first insulating film, a step of irradiating the second insulating film with first ions to form a separation layer in the single-crystal semiconductor substrate, a step of irradiating the second insulating film with second ions so that halogen is contained in the first insulating film, and a step of performing heat treatment to separate the single-crystal semiconductor substrate with a single-crystal semiconductor film left over the supporting substrate.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tetsuya Kakehata
  • Patent number: 8895413
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 25, 2014
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Peter De Dobbelaere, Sherif Abdalla, Daniel Kucharski, Gianlorenzo Masini, Kosei Yokoyama, John Guckenberger, Attila Mekis
  • Patent number: 8896062
    Abstract: The invention provides a semiconductor device, including: a semiconductor base, on an insulation layer; source/drain regions abutting opposite first sides of the semiconductor base; and gates at opposite second sides of the semiconductor base, wherein the semiconductor base includes a cavity, and the insulation layer is exposed by the cavity. The invention also provides a method for forming a semiconductor device, including: forming a semiconductor bottom on an insulation layer; forming source/drain regions, the source/drain regions abutting opposite first sides of the semiconductor bottom; forming gates on opposite second sides of the semiconductor bottom; and removing a part of the semiconductor bottom to form a cavity in the semiconductor bottom, the cavity exposing the insulation layer. With the technical solutions provided by the invention, short-channel effects can be alleviated, and the resistance of the source/drain regions and parasitic capacitance can be reduced.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 25, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 8884370
    Abstract: Narrow-body FETs, such as, FinFETs and trigates, exhibit superior short-channel characteristics compared to thick-body devices, such as planar bulk Si FETs and planar partially-depleted SOI (PDSOI) FETs. A common problem, however, with narrow-body devices is high series resistance that often negates the short-channel benefits. The high series resistance is due to either dopant pile-up at the SOI/BOX interface or dopant diffusion into the BOX. This disclosure describes a novel narrow-body device geometry that is expected to overcome the high series resistance problem.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: November 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Amlan Majumdar, Lidija Sekaric
  • Patent number: 8877604
    Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8877606
    Abstract: A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, David R. Greenberg, Amlan Majumdar, Leathen Shi, Jeng-Bang Yau
  • Patent number: 8866227
    Abstract: A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Stephen W. Bedell, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 8859347
    Abstract: Embodiments of the present invention provide for the removal of excess carriers from the body of active devices in semiconductor-on-insulator (SOI) structures. In one embodiment, a method of fabricating an integrated circuit is disclosed. In one step, an active device is formed in an active layer of a semiconductor-on-insulator wafer. In another step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In another step, an insulator material is removed from a back side of the SOI wafer to form an excavated insulator region. In another step, a conductive layer is deposited on the excavated insulator region. Depositing the conductive layer puts it in physical contact with a body of an active device in a first portion of the excavated insulator region. The conductive layer then couples the body to a contact in a second detached portion of the excavated insulator region.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: October 14, 2014
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Michael A. Stuber, Stuart B. Molin, Paul A. Nygaard
  • Patent number: 8841701
    Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 8835236
    Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8836032
    Abstract: According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: September 16, 2014
    Assignee: Broadcom Corporation
    Inventors: Wei Xia, Xiangdong Chen
  • Patent number: 8829967
    Abstract: Embodiments include an apparatus, system, and method related to a body-contacted partially depleted silicon on insulator (PDSOI) transistor that may be used in a switch circuit. In some embodiments, the switch circuit may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 9, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: George Nohra
  • Patent number: 8823104
    Abstract: Methods and structures for semiconductor devices with STI regions in SOI substrates is provided. A semiconductor structure comprises an SOI epitaxy island formed over a substrate. The structure further comprises an STI structure surrounding the SOI island. The STI structure comprises a second epitaxial layer on the substrate, and a second dielectric layer on the second epitaxial layer. A semiconductor fabrication method comprises forming a dielectric layer over a substrate and surrounding a device fabrication region in the substrate with an isolation trench extending through the dielectric layer. The method also includes filling the isolation trench with a first epitaxial layer and forming a second epitaxial layer over the device fabrication region and over the first epitaxial layer. Then a portion of the first epitaxial layer is replaced with an isolation dielectric, and then a device such as a transistor is formed second epitaxial layer within the device fabrication region.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Tze-Liang Lee, Pang-Yen Tsai
  • Patent number: 8822998
    Abstract: An organic light emitting display device includes a substrate, a plurality of sub-pixels on the substrate, each sub-pixel including a first region configured to emit light and a second region configured to transmit external light, a plurality of thin film transistors disposed in the first region of the each sub-pixel, a plurality of first electrodes disposed in the first region of each sub-pixel and electrically connected to the thin film transistors, a first insulating layer on at least a portion of the first region of each sub-pixel to cover a portion of the first electrode, an organic emission layer on the first electrode, a second insulating layer on at least a portion of the second region of each sub-pixel, the second insulating layer including a plurality of openings therein, and a second electrode covering the organic emission layer, the first insulating layer, and the second insulating layer.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong-Min Kim, Jun-Ho Choi, Jin-Koo Chung
  • Patent number: 8816437
    Abstract: Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Kazushige Hotta
  • Patent number: 8816344
    Abstract: A thin-film transistor includes a structure for protecting an active layer, and an organic light-emitting display device including the thin-film transistor.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Do-Hyun Kwon, Il-Jeong Lee, Choong-Youl Im, Ju-Won Yoon
  • Patent number: 8796769
    Abstract: A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Applied Matierials, Inc.
    Inventors: Dean C. Jennings, Amir Al-Bayati
  • Patent number: 8796811
    Abstract: In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: August 5, 2014
    Assignee: Oracle International Corporation
    Inventors: Ivan Shubin, Ashok V. Krishnamoorthy, John E. Cunningham
  • Patent number: 8796772
    Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Peter J. Vandervoorn, Walid M. Hafez, Chia-Hong Jan, Curtis Tsai, Joodong Park
  • Patent number: 8796695
    Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 5, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8796768
    Abstract: In an organic light-emitting display device and a method of manufacturing the same, the display device may include: a thin-film transistor including an active layer, a gate electrode including a first electrode which includes nano-Ag on an insulating layer formed on the active layer and a second electrode on the first electrode, a source electrode, and a drain electrode; an organic light-emitting device including a pixel electrode electrically connected to the thin-film transistor and formed of the same layer as, and using the same material used to form, the first electrode, an intermediate layer including an emissive layer, and an opposite electrode covering the intermediate layer and facing the pixel electrode; and a pad electrode formed of the same layer as, and using the same material used to form, the first electrode in a pad area located outside of a light-emitting area.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Chun-Gi You