Combined With Thin-film Or Thick-film Passive Component (epo) Patents (Class 257/E27.113)
  • Patent number: 9035417
    Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 19, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: David Reusch, Johan Tjeerd Strydom
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9035312
    Abstract: A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: May 19, 2015
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 8829527
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8823009
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8809996
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 8709890
    Abstract: An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8698251
    Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer on the substrate, the semiconductor layer including an impurity-doped polycrystalline silicon layer, a first capacitor electrode on the substrate main body, the first capacitor electrode including an impurity-doped polycrystalline silicon layer, and bottom surfaces of the first capacitor electrode and semiconductor layer facing the substrate main body being substantially coplanar, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, bottom surfaces of the second capacitor electrode and gate electrode facing the substrate main body being substantially coplanar, and the second capacitor electrode having a smaller thickness than the gate electrode.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Oh-Seob Kwon, Moo-Soon Ko
  • Patent number: 8692259
    Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 8, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Patent number: 8659154
    Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Jens Pohl
  • Patent number: 8575720
    Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Salvatore Coffa, Claudia Caligiore, Francesca Paola Tramontana
  • Publication number: 20130270650
    Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Inventors: Chi-Sheng Tseng, Yao-Chang Wang, Jie-Ning Yang
  • Patent number: 8546901
    Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eric R. Fossum, Dae-Kil Cha, Young-Gu Jin, Yoon-Dong Park, Soo-Jung Hwang
  • Patent number: 8531002
    Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 10, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Andrei Papou
  • Patent number: 8486796
    Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: David L. Harmon, Joseph M. Lukaitis, Stewart E. Rauch, III, Robert R. Robison, Dustin K. Slisher, Jeffrey H. Sloan, Timothy D. Sullivan, Kimball M. Watson
  • Patent number: 8461662
    Abstract: A carbon/epoxy composition includes a bisphenol-based epoxy, an amine-based curing agent, an imidazole-based curing catalyst, and carbon black. A carbon-epoxy dielectric layer is fabricated using a reaction product of the carbon/epoxy composition.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Lee, Jin-Young Bae, Yoo-Seong Yang, Sang-Soo Jee
  • Publication number: 20130126979
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Kuoyuan (Peter) HSU
  • Patent number: 8409887
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: April 2, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 8400577
    Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: March 19, 2013
    Assignee: Sony Corporation
    Inventors: Mitsuru Asano, Seiichiro Jinta, Masatsugu Tomida, Hiroshi Fujimura
  • Patent number: 8368150
    Abstract: In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude ?F, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: February 5, 2013
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Patent number: 8362562
    Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: January 29, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Masao Okihara
  • Patent number: 8357556
    Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method may include the steps of providing an active semiconductor device on a surface of a semiconductor substrate where the active device is surrounded by an inactive semiconductor area, and providing a soft metallic guard element in the inactive semiconductor area around at least a portion of the periphery of the active device wherein the metallic guard element is connected to ground potential and not to the active device.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: January 22, 2013
    Assignee: Emcore Corporation
    Inventors: Richard Carson, Elaine Taylor, Douglas Collins
  • Patent number: 8324628
    Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-il Kim, I-hun Song, Young-soo Park, Dong-hun Kang, Chang-jung Kim, Jae-chul Park
  • Patent number: 8304769
    Abstract: An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity. The gate electrode of each transistor and a gate insulating film covering the conductor have a thin section with reduced thickness, in an on-conductor area overlapping the conductor. At least a part of the thin section overlaps the capacity electrode. In this way, the active matrix substrate which can reduce inconsistency in capacitance values of capacities (e.g. a storage capacitor, a capacity for controlling an electric potential of a pixel electrode, and a capacity which can function as both of them) provided in the substrate.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 6, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihide Tsubata, Masanori Takeuchi
  • Patent number: 8269221
    Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 18, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ping Mei, Albert Jeans, Carl Taussig
  • Patent number: 8217396
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: July 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8198636
    Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 12, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Patent number: 8183568
    Abstract: A substrate for a semiconductor device includes: a base substrate; a semiconductor layer that has a source region, a drain region, a plurality of channel regions, and at least one intermediate region; a source electrode being in contact with the source region; a drain electrode being in contact with the drain region; a gate electrode that overlaps the plurality of channel regions, the intermediate region, and each of a part of the source electrode and a part of the drain electrode; and a floating electrode being in contact with the intermediate region. The size of an area where the floating electrode and the gate electrode overlap each other is smaller than the sum of the size of an area where the source electrode and the gate electrode overlap each other and the size of an area where the drain electrode and the gate electrode overlap each other.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 22, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Yasushi Yamazaki
  • Patent number: 8184224
    Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: May 22, 2012
    Assignee: Sony Corporation
    Inventors: Mitsuru Asano, Seiichiro Jinta, Masatsugu Tomida, Hiroshi Fujimura
  • Patent number: 8183661
    Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 22, 2012
    Assignee: Broadcom Corporation
    Inventor: Wenkwei Lou
  • Patent number: 8120111
    Abstract: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: February 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuji Yamaguchi, Kengo Akimoto, Hiroki Kayoiji, Toru Takayama
  • Patent number: 8115278
    Abstract: A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width direction); an insulator with a width b formed to be in contact with a side wall of the electrodes and an insulator formed in a region between the electrodes divided into a plurality of parts; a silicide layer formed over part of the surface of the impurity region; and characteristics of the TFT are evaluated by measuring resistance of the semiconductor film of the semiconductor element.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: February 14, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsuo Isobe
  • Patent number: 8097486
    Abstract: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: January 17, 2012
    Assignee: Sony Corporation
    Inventors: Hideo Kido, Kazuichiro Itonaga, Kai Yoshitsugu, Kenichi Chiba
  • Patent number: 8084798
    Abstract: A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Koike
  • Patent number: 8049257
    Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: November 1, 2011
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang Gi Lee
  • Patent number: 8043950
    Abstract: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Publication number: 20110254125
    Abstract: A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.
    Type: Application
    Filed: May 16, 2008
    Publication date: October 20, 2011
    Inventors: Daisuke Nomasaki, Koji Oka, Toshiaki Ozeki
  • Patent number: 8026116
    Abstract: Disclosed herein is a display device, including a display element, a first scanning line, a second scanning line, a data signal line, a switching element having a first terminal and a second terminal of a first conduction type, the first terminal being connected to the data signal line, for being held in a conducting state or a non-conducting state according to a voltage applied to the first scanning line, and a storage capacitance having a first electrode and a second electrode that shares the second scanning line, wherein the second terminal of the switching element is connected to the display element and connected to the first electrode of the storage capacitance including a semiconductor film of a second conduction type different from the second terminal.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: September 27, 2011
    Assignee: Sony Corporation
    Inventor: Tsutomu Tanaka
  • Publication number: 20110220906
    Abstract: The present invention discloses pixel structures and fabrication methods thereof. The pixel includes a thin film transistor forming at a thin film transistor region and a storage capacitor forming at a pixel electrode region. The method includes: forming a gate conduction layer on a substrate; forming a gate insulation layer on the gate conduction layer; forming a source conduction layer and a drain conduction layer on the gate insulation layer, in which the drain conduction layer has an extension section extending to the pixel electrode region; forming a channel layer on the source conduction layer and the drain conduction layer; and forming a protection layer on the channel layer. The extension section and an electrode layer serve as the upper and lower electrode of the storage capacitor, respectively. Wherein the gate conduction layer, the source conduction layer, the drain conduction layer, and the channel layer are made of metallic oxides.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 15, 2011
    Applicant: PRIME VIEW INTERNATIONAL CO., LTD.
    Inventors: SUNG-HUI HUANG, HENRY WANG, FANG AN SHU, TED-HONG SHINN
  • Patent number: 7994000
    Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: August 9, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Publication number: 20110180859
    Abstract: A semiconductor device includes a gate electrode formed on a substrate with a gate insulating layer in between, an insulating layer of property and thickness that allow for a silicide block formed in a first region of the substrate so as to cover the gate electrode, a sidewall formed to at least partly include the insulating layer at a side of the gate electrode, a first impurity region formed by implantation of a first impurity in a peripheral region of the gate electrode formed in the first region of the substrate before the insulating layer is formed, a second impurity region formed by implantation of a second impurity in a peripheral region of the sidewall of the gate electrode formed in a second region of the substrate after the sidewall is formed, and a silicide layer formed on a surface of the second impurity region of the substrate.
    Type: Application
    Filed: December 15, 2010
    Publication date: July 28, 2011
    Applicant: Sony Corporation
    Inventor: Keiji Tatani
  • Patent number: 7952094
    Abstract: An electro-optical device including a substrate, data lines and scanning lines, thin film transistors being disposed below the data lines and above the substrate. Storage capacitors are disposed over the data lines in a region opposite to the channel region of the thin film transistors in plan view. Each storage capacitor has a pixel-potential-side electrode, a dielectric film, and a fixed-potential-side electrode that have been formed sequentially. The pixel electrodes are disposed over the storage capacitors so as to correspond to the data lines and the scanning lines on the substrate in plan view, and the pixel electrodes are electrically connected to the pixel-potential-side electrodes and the thin film transistors. This abstract is intended only to aid those searching patents, and is not intended to be used to interpret or limit the scope or meaning of the claims in any manner.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 31, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Yasuji Yamasaki
  • Patent number: 7947979
    Abstract: An object of the invention is to manage variation of electrical characteristics of an element in a semiconductor device due to a vapor deposition process by measuring electrical characteristics of a TEG. A substrate 100 of an active matrix EL panel includes a vapor deposition region 101 having a film formed by a vapor deposition method. In the vapor deposition region 101, a pixel region 102 is provided. A TEG 109 is provided in the vapor deposition region 101 having a film formed in a vapor deposition step and outside of the pixel region 102. A measurement terminal portion 110 for measuring the TEG 109 is provided outside of a sealing region 103.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryo Arasawa, Tomoyuki Iwabuchi
  • Patent number: 7944016
    Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: May 17, 2011
    Assignee: Broadcom Corporation
    Inventor: Wenkwei Lou
  • Publication number: 20110101351
    Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.
    Type: Application
    Filed: October 27, 2010
    Publication date: May 5, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 7880268
    Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: February 1, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Sébastien Cremer, Cédric Perrot, Claire Richard
  • Patent number: 7872264
    Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: January 18, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Publication number: 20100327355
    Abstract: This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Application
    Filed: September 8, 2010
    Publication date: December 30, 2010
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7855089
    Abstract: A method for manufacture of application specific solar cells includes providing and processing custom design information to determine at least a cell size and a cell shape. The method includes providing a transparent substrate having a back surface region, a front surface region, and one or more grid-line regions overlying the front side surface region. The one or more grid regions provide one or more unit cells having the cell size and the cell shape. The method further includes forming a layered structure including photovoltaic materials overlying the front surface region.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: December 21, 2010
    Assignee: Stion Corporation
    Inventors: Chester A. Farris, III, Albert S. Brown
  • Patent number: 7800139
    Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: September 21, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Bo Hyun Lee, Tae Hyoung Moon, Jae Hyun Kim