Combined With Thin-film Or Thick-film Passive Component (epo) Patents (Class 257/E27.113)
  • Patent number: 11937456
    Abstract: A display apparatus includes a substrate including a display area for displaying an image, a first thin film transistor in the display area and including a first semiconductor layer having a silicon semiconductor and a first gate electrode insulated from the first semiconductor layer, a first interlayer insulating layer covering the first gate electrode and having a first contact hole extending therethrough, and a second thin film transistor on the first interlayer insulating layer and including a second semiconductor layer having an oxide semiconductor and a second gate electrode insulated from the second semiconductor layer. A portion of the second semiconductor layer extends into a first contact hole and is electrically connected to the first semiconductor layer.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kiwook Kim, Chul kyu Kang, Wonkyu Kwak, Kwangmin Kim, Joongsoo Moon
  • Patent number: 11910650
    Abstract: A display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulation layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulation layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulation layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulation layer, the capacitor electrode overlapping the first gate electrode, wherein a permittivity of the first gate insulation layer is greater than a permittivity of the buffer layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Woo Lee, Jintaek Kim, Yeonhong Kim, Pilsuk Lee
  • Patent number: 11901451
    Abstract: A method of fabricating a semiconductor device is described. A first material layer is formed, wherein the first material layer contains crystalline aluminum nitride or aluminum scandium nitride (AlScN) with a first Sc content. A second material layer is formed on the first material layer, wherein the second material layer contains aluminum scandium nitride (AlScN) with a second Sc content higher than the first Sc content. A third material layer is formed on the second material layer, wherein the third material layer contains aluminum scandium (AlSc).
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Georgios Vellianitis
  • Patent number: 11894388
    Abstract: The application discloses a method adapted to manufacture an array substrate and a display panel. The method includes: forming a photoresist layer, a source and a drain; post-baking the photoresist layer, so that the photoresist layer flows to the position of a channel; etching a semiconductor layer to obtain a preset pattern; and peeling off the photoresist layer.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 6, 2024
    Assignee: HKC CORPORATION LIMITED
    Inventor: Bei Zhou Huang
  • Patent number: 11889743
    Abstract: The present disclosure discloses an evaporation method, an evaporation mask assembly, a display panel and a display device, which can reduce the complexity of the manufacturing process of the display panel and improve the yield of the display panel. The evaporation method may comprise: performing a first evaporation on a base substrate by using a first mask to form a first evaporation sub-pattern on the base substrate, wherein the first mask has a first opening area; and performing a second evaporation on the base substrate by using a second mask to form a second evaporation sub-pattern on the base substrate, wherein the second mask has a second opening area; wherein the combination of the first and second evaporation sub-patterns forms an evaporation pattern.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: January 30, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuwu Hu, Yangsheng Liu, Mengxia Kong, Donghui Si, Shan Mou, Yan Cui, Yu Wang
  • Patent number: 11887942
    Abstract: A package structure for a power supply module, can include: a die and a capacitive element that are separated from each other and arranged on different horizontal planes with different heights along a vertical direction of the package structure; connection structures that connect to the die and to the capacitive element; where a current loop comprising at least two parallel current paths on different horizontal planes with different heights along the vertical direction of the package structure is formed; and where the current loop passes through the die, the capacitive element, and the connection structures, and directions of currents of the two parallel current paths are at least partially opposite to each other in order to decrease electromagnetic interference.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: January 30, 2024
    Assignee: Hefei Silergy Semiconductor Technology Co., Ltd.
    Inventors: Ke Dai, Jian Wei, Jiajia Yan
  • Patent number: 11881185
    Abstract: A display module is provided. The display module includes a main display panel, an auxiliary display panel and a backlight module which are laminated sequentially, at least one temperature sensing circuit in the auxiliary display panel, and a control circuit coupled to the at least one temperature sensing circuit. The temperature sensing circuit is configured to generate, based on temperature of the auxiliary display panel, a temperature signal related to the temperature, and the control circuit is configured to adjust a display parameter of the main display panel based on the temperature signal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 23, 2024
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hui Yu, Xin Fang, Kai Diao, Jie Liu, Chengkun Liu, Xin Chen
  • Patent number: 11862378
    Abstract: A resonant coil with integrated capacitance includes at least one separation dielectric layer and a plurality of conductor layers stacked in an alternating manner. Each of the plurality of conductor layers includes a first conductor sublayer and second conductor sublayer having common orientation and a sublayer dielectric layer separating the first and second conductor sublayers. Adjacent conductor layers of the plurality of conductor layers have different orientations.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 2, 2024
    Inventors: Charles R. Sullivan, Aaron L. F. Stein, Phyo Aung Kyaw
  • Patent number: 11839134
    Abstract: A display device is provided. The display device includes a first substrate, a first detection electrode on the first substrate, a first bank including an opening that exposes the first detection electrode, a photosensitive layer on the first detection electrode, a second detection electrode on the photosensitive layer, a first electrode on the second detection electrode, a second bank including an opening that exposes the first electrode, a light emitting layer on the first electrode, a second electrode on the light emitting layer, a first optical system between the second detection electrode and the first electrode, and a second optical system on the second electrode, wherein the first optical system and the second optical system overlap the photosensitive layer in a thickness direction of the display device.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: December 5, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Suk Kim, Yu Na Kim, Soo Jung Lee, Keum Dong Jung, Go Eun Cha
  • Patent number: 11832482
    Abstract: A double-sided emissive transparent organic light-emitting diode display and method of manufacturing the same are provided. A double-sided emissive transparent organic light-emitting diode display includes: a substrate, a plurality of pixel areas, each including, on the substrate: a light transmitting area, and a light-emitting area, the light-emitting area including: a bottom light-emitting area including a bottom-emissive organic light-emitting diode, and a top light-emitting area including: a top-emissive organic light-emitting diode, a plurality of bottom driving elements under the top-emissive organic light-emitting diode, the bottom driving elements being configured to drive the bottom-emissive organic light-emitting diode, and a plurality of top driving elements under the top-emissive organic light-emitting diode, the top driving elements being configured to drive the top-emissive organic light-emitting diode.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 28, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Taehan Kim, Binn Kim
  • Patent number: 11823977
    Abstract: A semiconductor device includes a substrate, a plurality of circuit elements on a front side of the substrate, and a first substantially spiral-shaped conductor on a back side of the substrate is provided. The device further includes a first through-substrate via (TSV) electrically connecting a first end of the substantially spiral-shaped conductor to a first one of the plurality of circuit elements, and a second TSV electrically connecting a second end of the substantially spiral-shaped conductor to a second one of the plurality of circuit elements. The device may be a package further including a second die having a front side on which is disposed a second substantially spiral-shaped conductor. The front side of the second die is disposed facing the back side of the substrate, such that the first and second substantially spiral-shaped conductors are configured to wirelessly communicate.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 21, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 11804192
    Abstract: A display module is provided. The display module includes a main display panel, an auxiliary display panel and a backlight module which are laminated sequentially, at least one temperature sensing circuit in the auxiliary display panel, and a control circuit coupled to the at least one temperature sensing circuit. The temperature sensing circuit is configured to generate, based on temperature of the auxiliary display panel, a temperature signal related to the temperature, and the control circuit is configured to adjust a display parameter of the main display panel based on the temperature signal.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 31, 2023
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hui Yu, Xin Fang, Kai Diao, Jie Liu, Chengkun Liu, Xin Chen
  • Patent number: 11804582
    Abstract: A light-emitting diode (LED) chip structure with a cup-like reflective element is provided. The LED chip structure comprises a substrate, an isolation element and a mesa including an LED surrounded by the isolation element. The isolation element comprises an upper isolation part and a lower isolation part. The lower isolation part is positioned in the substrate and the upper isolation part protrudes from a surface of the substrate. A reflective layer is disposed on a sidewall of the upper isolation part, and a bottom of the reflective layer does not contact the mesa. The cup-like reflective element at least includes the isolation element with the reflective layer.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: October 31, 2023
    Assignee: Jade Bird Display (Shanghai) Limited
    Inventor: Qiming Li
  • Patent number: 11796875
    Abstract: A display component includes a display panel. The display panel includes an array substrate and a counter substrate, and the display panel includes a display region, where the display region includes a pixel region, a transparent region, and a light shielding region. A first light shielding pattern located in the light shielding region is disposed on a side that is of the array substrate and that is away from the counter substrate, and the first light shielding pattern is disposed around the transparent region.
    Type: Grant
    Filed: November 30, 2019
    Date of Patent: October 24, 2023
    Assignee: Honor Device Co., Ltd.
    Inventors: Bin Yan, Yan Lv, Yankai Niu, Bangshi Yin
  • Patent number: 11798493
    Abstract: A display device including: a pixel connected to a scan line and a data line intersecting the scan line. The pixel includes a light emitting element and a driving transistor which controls a driving current supplied to the light emitting element according to a data voltage applied from the data line. The driving transistor includes a first active layer including an oxide semiconductor doped with a metal.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 24, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myoung Hwa Kim, Masataka Kano, Yeon Keon Moon, Joon Seok Park, Jun Hyung Lim, Hye Lim Choi
  • Patent number: 11791414
    Abstract: The embodiments of the present invention provide a thin film transistor (TFT) device, a manufacturing method thereof, and an array substrate. A gate electrode comprises a first sub-gate electrode and a second sub-gate electrode disposed on different layers. The first sub-gate electrode is located between the active layer, the source electrode, and the drain electrode in a film thickness direction of the TFT device. The second sub-gate electrode, the source electrode, and the drain electrode are disposed on a same layer. The second sub-gate electrode comprises two gate electrode metal patterns. The two gate electrode metal patterns are spaced apart and electrically connected to a same scan line and simultaneously charge the first sub-gate electrode.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 17, 2023
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jianlong Huang
  • Patent number: 11793060
    Abstract: An OLED display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to transfer a scan signal, a data line and a driving voltage line crossing the scan line and respectively configured to transfer a data voltage and a driving voltage, and a switching transistor electrically connected to the scan line and the data line and including a switching drain electrode configured to output the data voltage. The display also includes a driving transistor including a driving gate electrode, a driving drain electrode, and a driving source electrode electrically connected to the switching drain electrode. The display further includes a storage capacitor including a first storage electrode electrically connected to the driving gate electrode and a second storage electrode formed on the same layer as the driving voltage line.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 17, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung Geun Cha, Jin Goo Jung, Yoon Ho Khang, Se Mi Kim
  • Patent number: 11754897
    Abstract: A liquid crystal display is provided and includes first and second substrates and liquid crystal layer therebetween; pixel electrode on first substrate; pedestal metal coupled to pixel electrode; semiconductor layer substantially U-shaped and coupled to pedestal metal at first coupling portion; scan line that extends in first direction and in layer different from semiconductor layer; signal line that extends in second direction different from first direction so as to three-dimensionally cross scan line, signal line being coupled to semiconductor layer at second coupling portion; and extending portion that is part of scan line and that protrudes from scan line, the extending portion extending along signal line, wherein: in first direction along a shorter side of each pixel unit, extending portion is adjacent to pedestal metal; and in second direction along a longer side of each pixel unit, length of extending portion is smaller than length of pedestal metal.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: September 12, 2023
    Assignee: Japan Display Inc.
    Inventor: Gen Koide
  • Patent number: 11757079
    Abstract: A display device includes a circuit substrate comprising a first electrode pad and an LED chip comprising a first electrode bump that is electrically connected to the first electrode pad, and at least emitting light in a direction of the circuit substrate. The first electrode pad comprises a first light transmission region that transmits light emitted from the LED chip.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: September 12, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventor: Akihiro Ogawa
  • Patent number: 11742360
    Abstract: A gate driver on array (GOA) array substrate, a method for fabricating the same, and a display device including the same, which include a GOA driving circuit. The GOA driving circuit includes a plurality of GOA units. Each of the GOA units includes a thin film transistor array layer, a first metal layer, an insulating layer, and a second metal layer. The first metal layer has a patterned signal line at a position crossing the second metal layer. The signal line includes a trunk portion and side walls formed of two opposite sides of the trunk portion. The side walls are shaped as arc-shaped grooves.
    Type: Grant
    Filed: May 9, 2020
    Date of Patent: August 29, 2023
    Inventor: Bangqing Xiao
  • Patent number: 11729967
    Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chung-Liang Cheng
  • Patent number: 11696477
    Abstract: An organic light emitting diode display includes: a substrate including a display area and a non-display area adjacent to the display area; a pixel thin film transistor positioned in the display area of the substrate; a first data wire positioned on the pixel thin film transistor; a second data wire positioned on the first data wire; an organic light emitting element positioned on the second data wire and electrically connected to the pixel thin film transistor through the first data wire and the second data wire; a circuit unit positioned in the non-display area of the substrate and including a circuit thin film transistor electrically connected to the pixel thin film transistor; and a common power supply line overlapping at least part of the circuit unit, electrically connected to the organic light emitting element, and formed on a same layer as the second data wire.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: July 4, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyong Tae Park, Sung Ho Cho, Seong Yeun Kang
  • Patent number: 11682692
    Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hua Lin, Hsun-Chung Kuang, Yu-Hsing Chang, Yao-Wen Chang
  • Patent number: 11675237
    Abstract: An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: June 13, 2023
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Maokun Tian, Zhonghao Huang, Xu Wu, Chengjun Qi, Jun Wang, Dan Liu
  • Patent number: 11665909
    Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bi-Shen Lee, Yi Yang Wei, Hsing-Lien Lin, Hsun-Chung Kuang, Cheng-Yuan Tsai, Hai-Dang Trinh
  • Patent number: 11664389
    Abstract: A thin film transistor substrate includes a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The first conductive layer is disposed on the substrate and includes a trace portion extending along a first direction and a protrusive portion extending from the trace portion. The second conductive layer is disposed on the first conductive layer and includes a wiring portion extending along a second direction. The trace portion has a first edge and a second edge opposite to the first edge, and the protrusive portion has at least one curved edge connecting with the second edge. When viewed in a third direction perpendicular to the first direction and the second direction, an interface disposes between the trace portion and the protrusive portion, a virtual extending line overlaps the second edge and the interface, and the semiconductor layer extends beyond the virtual extending line.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 30, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Cheng-Hsiung Chen, Pei-Chieh Chen, Chao-Hsiang Wang, Yi-Ching Chen
  • Patent number: 11637133
    Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate includes an active island and a gate insulating layer, a gate, and an interlayer dielectric layer stacked on the active island. A color resist layer is disposed on the interlayer dielectric layer, and an orthographic projection of the color resist layer on a base substrate covers an orthographic projection of a channel region of the active island on the base substrate.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 25, 2023
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hui He
  • Patent number: 11630333
    Abstract: Display panel and display device are provided. The display panel includes a plurality of pixels and a blocking metal wire. The pixel includes a display unit and a control unit driving the display unit. The display unit at least includes a heating element and a phase change material layer. The heating element includes a first connecting terminal and a second connecting terminal. The control unit includes a first signal terminal and a second signal terminal. The control unit includes at least one diode, which includes a diode semiconductor layer including a first electrode contact region, a second electrode contact region and a connecting region. The blocking metal wire covers the connecting region and is insulated from the connecting region. The blocking metal wire is electrically connected to each of the first signal terminal and the first signal source or to each of the second connecting terminal and the second signal source.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: April 18, 2023
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Shaolong Ma, Feng Lu, Qijun Yao
  • Patent number: 11592618
    Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsing-Kuo Hsia, Chen-Hua Yu, Kuo-Chiang Ting, Shang-Yun Hou
  • Patent number: 11581358
    Abstract: According to one embodiment, an optical sensor device includes an insulating substrate, a first conductive layer and an optical sensor element disposed between the insulating substrate and the first conductive layer. The optical sensor element is electrically connected to the first conductive layer and covered by the first conductive layer. The optical sensor element includes a first semiconductor layer formed of an oxide semiconductor and controls an amount of charge flowing to the first conductive layer according to an amount of incident light to the first semiconductor layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: February 14, 2023
    Assignee: Japan Display Inc.
    Inventors: Takanori Tsunashima, Masashi Tsubuku, Makoto Uchida
  • Patent number: 11569334
    Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a first reference voltage line, a second reference voltage line and a first reference voltage auxiliary line, the first reference voltage line, the second reference voltage line and the first reference voltage auxiliary line are respectively disposed in one of a second wiring layer, a third wiring layer and a fourth wiring layer, the first reference voltage line is electrically coupled to the first reference voltage auxiliary line through via holes penetrating an insulating layer therebetween, the first reference voltage line and the first reference voltage auxiliary line extend in different directions, the second reference voltage line and the first reference voltage auxiliary line extend in a same direction, the first reference voltage line extends in a row or column direction, and the second reference voltage line extends in the row or column direction.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 31, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Wang, Libin Liu
  • Patent number: 11545539
    Abstract: There is provided a display device. The display device includes a first data line on a first interlayer insulating layer over a substrate, a first power line and a second power line on a second interlayer insulating layer, the second interlayer insulating layer covering the first data line, and a plurality of pixels. A first pixel among the plurality of pixels includes a display element including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, the second power line being connected to the opposite electrode, and a driving thin film transistor between the substrate and the display element and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covering the driving gate electrode, and the first power line being connected to the driving source electrode.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kangmoon Jo, Dongwoo Kim, Sungjae Moon, Junhyun Park, Ansu Lee
  • Patent number: 11515377
    Abstract: Disclosed herein is a display panel, comprising: a support; a first layer comprising a light emitter, a first region and a second region; a second layer sandwiched between the first layer and the support; wherein the first region and the second region allow light scattered by an object (e.g., a person's finger) to transmit therethrough; wherein the second layer allows light transmitted through the first region to reach the support and comprises a light-blocking layer configured to attenuate light transmitted through the second region.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 29, 2022
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Kuo Sun, Hai Zheng, Jianxiong Huang, Guodong Liu
  • Patent number: 11489024
    Abstract: A display device comprises a substrate including display and peripheral areas, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is disposed in the display area on the substrate, and the pixel structure is disposed on the semiconductor element. The dummy patterns which have stacked structure are disposed in the peripheral area on the substrate, and contain a material identical to a material constituting the semiconductor element. The dummy patterns are arranged in a grid shape in different layers, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of dummy patterns which are adjacent to each other in the different layers among the dummy patterns are overlapped each other in a direction from the substrate to the pixel structure.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 1, 2022
    Inventors: Sewan Son, Moo Soon Ko, Ji Ryun Park, Jin Sung An, Min Woo Woo, Seong Jun Lee, Wang Woo Lee, Jeong-Soo Lee, Ji Seon Lee, Deuk Myung Ji
  • Patent number: 11404672
    Abstract: The present disclosure provides a display panel, manufacturing method thereof, and a display device. The display panel includes a substrate, a functional layer formed on the substrate, and an encapsulation layer formed on the functional layer. The encapsulation layer includes an inorganic layer on the functional layer, the inorganic layer includes a first oxide layer and a second oxide layer, and a ratio of the number of atomic layers of the first oxide layer to the number of atomic layers of the second oxide layer ranges from 1:4 to 3:1.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 2, 2022
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventors: Ping Zhu, Shengfang Liu, Xueyuan Li, Ying Huang
  • Patent number: 11393858
    Abstract: An imaging device includes a semiconductor substrate including a semiconductor region including an impurity of a first conductivity type, a first diffusion region that is in contact with the semiconductor region, that includes an impurity of a second conductivity type, and that converts incident light into charges, and a second diffusion region that includes an impurity of the second conductivity type and that accumulates at least a part of the charges flowing from the first diffusion region, a first transistor that includes a first gate electrode and that includes the second diffusion region as one of a source and a drain, a contact plug electrically connected to the second diffusion region, a capacitive element one end of which is electrically connected to the contact plug, and a second transistor that includes a second gate electrode, the second gate electrode being electrically connected to the one end of the capacitive element.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: July 19, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junji Hirase, Yoshihiro Sato, Yasuyuki Endoh, Hiroyuki Amikawa
  • Patent number: 11372296
    Abstract: A liquid crystal display is provided and includes first and second substrates and liquid crystal layer therebetween; pixel electrode on first substrate; pedestal metal coupled to pixel electrode; semiconductor layer substantially U-shaped and coupled to pedestal metal at first coupling portion; scan line that extends in first direction and in layer different from semiconductor layer; signal line that extends in second direction different from first direction so as to three-dimensionally cross scan line, signal line being coupled to semiconductor layer at second coupling portion; and extending portion that is part of scan line and that protrudes from scan line, the extending portion extending along signal line, wherein: in first direction along a shorter side of each pixel unit, extending portion is adjacent to pedestal metal; and in second direction along a longer side of each pixel unit, length of extending portion is smaller than length of pedestal metal.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 28, 2022
    Assignee: Japan Display Inc.
    Inventor: Gen Koide
  • Patent number: 11372299
    Abstract: A display panel includes a first substrate; a scan line and a data line disposed on the first substrate and extending in a first direction and a second direction, respectively, wherein the data line intersects the scan line; a polysilicon layer disposed on the first substrate. In a top view, the polysilicon layer includes: a first channel region overlapping a portion of the scan line; a second channel region overlapping another portion of the scan line; a non-channel region not overlapping the scan line and connected between the first channel region and the second channel region; a long region extended in the second direction; wherein a portion of the non-channel region extends in the first direction, the portion has a first width in the second direction, the long region has a second width in the first direction, and the first width is greater than the second width.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: June 28, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Hsing-Yi Liang, Kuei-Ling Liu, Te-Yu Lee
  • Patent number: 11367774
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, where the substrate includes a shielding region having a first area; a first shielding layer on the substrate, where a first shielding structure is in the first shielding layer of the shielding region, and the first shielding structure has a first density; a second shielding layer on the first shielding layer, where a second shielding structure is in the second shielding layer of the shielding region, and the second shielding structure has a second density which is less than the first density; and an electrical interconnection structure, electrically interconnecting the first shielding structure with the second shielding structure and enabling the first shielding structure grounded.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: June 21, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9035312
    Abstract: A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: May 19, 2015
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 9035417
    Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 19, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: David Reusch, Johan Tjeerd Strydom
  • Patent number: 8829527
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8823009
    Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Motomu Kurata, Hiroyuki Hata, Mitsuhiro Ichijo, Takashi Ohtsuki, Aya Anzai, Masayuki Sakakura
  • Patent number: 8809996
    Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Li-Hsien Huang
  • Patent number: 8709890
    Abstract: An ETSOI transistor and a combination of capacitors, junction diodes, bank end contacts and resistors are respectively formed in a transistor and capacitor region thereof by etching through an ETSOI and BOX layers in a replacement gate HK/MG flow. The capacitor and other devices formation are compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor, and devices. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Thomas N. Adam, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8698251
    Abstract: An organic light emitting diode display includes a substrate, a semiconductor layer on the substrate, the semiconductor layer including an impurity-doped polycrystalline silicon layer, a first capacitor electrode on the substrate main body, the first capacitor electrode including an impurity-doped polycrystalline silicon layer, and bottom surfaces of the first capacitor electrode and semiconductor layer facing the substrate main body being substantially coplanar, a gate insulating layer on the semiconductor layer and the first capacitor electrode, a gate electrode on the semiconductor layer with the gate insulating layer therebetween, and a second capacitor electrode on the first capacitor electrode with the gate insulating layer therebetween, bottom surfaces of the second capacitor electrode and gate electrode facing the substrate main body being substantially coplanar, and the second capacitor electrode having a smaller thickness than the gate electrode.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Oh-Seob Kwon, Moo-Soon Ko
  • Patent number: 8692259
    Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: April 8, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Patent number: 8659154
    Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Jens Pohl
  • Patent number: 8575720
    Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Leonardi, Salvatore Coffa, Claudia Caligiore, Francesca Paola Tramontana