Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.

Abstract: A process is described for integrating, on an inert substrate, a device having at least one passive component and one active component. The process comprises: deposition of a protection dielectric layer on the inert substrate; formation of a polysilicon island on the protection dielectric layer; integration of the active component on the polysilicon island; deposition of the covering dielectric layer on the protection dielectric layer and on the active component; integration of the passive component on the covering dielectric layer; formation of first contact structures in openings realised in the covering dielectric layer in correspondence with active regions of the active component; and formation of second contact structures in correspondence with the passive component. An integrated device obtained through this process is also described.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure.

Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.

Abstract: A carbon/epoxy composition includes a bisphenol-based epoxy, an amine-based curing agent, an imidazole-based curing catalyst, and carbon black. A carbon-epoxy dielectric layer is fabricated using a reaction product of the carbon/epoxy composition.

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.

Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

Abstract: In the present invention, discrete decoupling capacitors are mounted on the surface of an IC chip. Since a discrete capacitor can provide the capacitance of the magnitude ?F, the attached capacitors can serve as the local power reservoir to decouple the external power ground noise caused by wirebonds, packages, and other system components.

Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.

Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method may include the steps of providing an active semiconductor device on a surface of a semiconductor substrate where the active device is surrounded by an inactive semiconductor area, and providing a soft metallic guard element in the inactive semiconductor area around at least a portion of the periphery of the active device wherein the metallic guard element is connected to ground potential and not to the active device.

Abstract: Provided is a channel layer for a thin film transistor, a thin film transistor and methods of forming the same. A channel layer for a thin film transistor may include IZO (indium zinc oxide) doped with a transition metal. A thin film transistor may include a gate electrode and the channel layer formed on a substrate, a gate insulating layer formed between the gate electrode and channel layer, and a source electrode and a drain electrode which contact ends of the channel layer.

Abstract: An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity. The gate electrode of each transistor and a gate insulating film covering the conductor have a thin section with reduced thickness, in an on-conductor area overlapping the conductor. At least a part of the thin section overlaps the capacity electrode. In this way, the active matrix substrate which can reduce inconsistency in capacitance values of capacities (e.g. a storage capacitor, a capacity for controlling an electric potential of a pixel electrode, and a capacity which can function as both of them) provided in the substrate.

Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.

Abstract: The present invention provides a method for manufacturing a highly reliable display device at a low cost with high yield. According to the present invention, a step due to an opening in a contact is covered with an insulating layer to reduce the step, and is processed into a gentle shape. A wiring or the like is formed to be in contact with the insulating layer and thus the coverage of the wiring or the like is enhanced. In addition, deterioration of a light-emitting element due to contaminants such as water can be prevented by sealing a layer including an organic material that has water permeability in a display device with a sealing material. Since the sealing material is formed in a portion of a driver circuit region in the display device, the frame margin of the display device can be narrowed.

Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: A substrate for a semiconductor device includes: a base substrate; a semiconductor layer that has a source region, a drain region, a plurality of channel regions, and at least one intermediate region; a source electrode being in contact with the source region; a drain electrode being in contact with the drain region; a gate electrode that overlaps the plurality of channel regions, the intermediate region, and each of a part of the source electrode and a part of the drain electrode; and a floating electrode being in contact with the intermediate region. The size of an area where the floating electrode and the gate electrode overlap each other is smaller than the sum of the size of an area where the source electrode and the gate electrode overlap each other and the size of an area where the drain electrode and the gate electrode overlap each other.

Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

Abstract: An object of the present invention is to provide a method for manufacturing a thin film transistor which enables heat treatment aimed at improving characteristics of a gate insulating film such as lowering of an interface level or reduction in a fixed charge without causing a problem of misalignment in patterning due to expansion or shrinkage of glass. A method for manufacturing a thin film transistor of the present invention comprises the steps of heat-treating in a state where at least a gate insulating film is formed over a semiconductor film on which element isolation is not performed, simultaneously isolating the gate insulating film and the semiconductor film into an element structure, forming an insulating film covering a side face of an exposed semiconductor film, thereby preventing a short-circuit between the semiconductor film and a gate electrode.

Abstract: A semiconductor element formed over the same substrate as a TFT, includes a semiconductor film having an impurity region; an insulating film formed over the semiconductor film; an electrode divided into a plurality of parts over the insulating film by spacing a distance a in a first direction (channel width direction); an insulator with a width b formed to be in contact with a side wall of the electrodes and an insulator formed in a region between the electrodes divided into a plurality of parts; a silicide layer formed over part of the surface of the impurity region; and characteristics of the TFT are evaluated by measuring resistance of the semiconductor film of the semiconductor element.

Abstract: There is provided a solid-state imaging element having a light receiving part generating charges by light irradiation, and a source/drain region of a transistor, both formed in a semiconductor layer. The solid-state imaging element includes a non-silicided region including the light receiving part, in which surfaces of the source/drain region and a gate electrode of the transistor are not silicided; and a silicided region in which the surfaces of the source/drain region and the gate electrode of the transistor are silicided. The non-silicided region has a sidewall formed on a side surface of the gate electrode of the transistor, a hydrogen supply film formed to cover the semiconductor layer, the gate electrode, and the sidewall, and a salicide block film formed on the hydrogen supply film to prevent silicidation. The silicided region has a sidewall formed on the side surface of the gate electrode of the transistor.

Abstract: A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area.

Abstract: Provided are a CMOS image sensor in which microlenses are formed in a remaining space in a patterned light shielding layer to improve image sensor characteristics and to protect the microlenses during packaging. The CMOS image sensor may include: a semiconductor substrate; at least one photodiode on or in the semiconductor substrate; a first insulating layer on the substrate including the photodiode(s); a plurality of metal lines on and/or in the first insulating layer; a second insulating layer on the first insulating layer including at least some of the metal lines; a patterned light shielding layer on the second insulating layer; and microlenses in a remaining space on the second insulating layer.

Abstract: It is an object of the present invention to manufacture a micromachine having a plurality of structural bodies with different functions and to shorten the time required for sacrifice layer etching in a process of manufacturing the micromachine. Another object of the present invention is to prevent a structural layer from being attached to a substrate after the sacrifice layer etching. In other words, an object of the present invention is to provide an inexpensive and high-value-added micromachine by improving throughput and yield. The sacrifice layer etching is conducted in multiple steps. In the multiple steps of the sacrifice layer etching, a part of the sacrifice layer that does not overlap with the structural layer is removed by the earlier sacrifice layer etching and a part of the sacrifice layer that is under the structural layer is removed by the later sacrifice layer etching.

Abstract: A semiconductor integrated circuit according to the present invention is equipped with a plurality of analog macros having comb capacitors (10), each comb capacitor (10) has a comb-shaped first electrode (11) and a comb-shaped second electrode (12), comb tooth portions (13) of the electrode (11) and comb tooth portions (14) of the electrode (12) are engaged so that the comb tooth portions (13) and the comb tooth portions (14) are arranged alternately and parallel to one another, and a comb tooth interval S of the comb capacitor is varied according to an absolute accuracy indicating an error between an actual capacitance value and an ideal capacitance value, or a relative accuracy indicating a difference in capacitance values between adjacent comb capacitors. Thereby, it is possible to provide a semiconductor integrated circuit which is equipped with highly-accurate analog macros and highly-integrated analog macros having comb capacitors which ensure high capacitance accuracies.

Abstract: Disclosed herein is a display device, including a display element, a first scanning line, a second scanning line, a data signal line, a switching element having a first terminal and a second terminal of a first conduction type, the first terminal being connected to the data signal line, for being held in a conducting state or a non-conducting state according to a voltage applied to the first scanning line, and a storage capacitance having a first electrode and a second electrode that shares the second scanning line, wherein the second terminal of the switching element is connected to the display element and connected to the first electrode of the storage capacitance including a semiconductor film of a second conduction type different from the second terminal.

Abstract: The present invention discloses pixel structures and fabrication methods thereof. The pixel includes a thin film transistor forming at a thin film transistor region and a storage capacitor forming at a pixel electrode region. The method includes: forming a gate conduction layer on a substrate; forming a gate insulation layer on the gate conduction layer; forming a source conduction layer and a drain conduction layer on the gate insulation layer, in which the drain conduction layer has an extension section extending to the pixel electrode region; forming a channel layer on the source conduction layer and the drain conduction layer; and forming a protection layer on the channel layer. The extension section and an electrode layer serve as the upper and lower electrode of the storage capacitor, respectively. Wherein the gate conduction layer, the source conduction layer, the drain conduction layer, and the channel layer are made of metallic oxides.

Abstract: To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film.

Abstract: A semiconductor device includes a gate electrode formed on a substrate with a gate insulating layer in between, an insulating layer of property and thickness that allow for a silicide block formed in a first region of the substrate so as to cover the gate electrode, a sidewall formed to at least partly include the insulating layer at a side of the gate electrode, a first impurity region formed by implantation of a first impurity in a peripheral region of the gate electrode formed in the first region of the substrate before the insulating layer is formed, a second impurity region formed by implantation of a second impurity in a peripheral region of the sidewall of the gate electrode formed in a second region of the substrate after the sidewall is formed, and a silicide layer formed on a surface of the second impurity region of the substrate.

Abstract: An electro-optical device including a substrate, data lines and scanning lines, thin film transistors being disposed below the data lines and above the substrate. Storage capacitors are disposed over the data lines in a region opposite to the channel region of the thin film transistors in plan view. Each storage capacitor has a pixel-potential-side electrode, a dielectric film, and a fixed-potential-side electrode that have been formed sequentially. The pixel electrodes are disposed over the storage capacitors so as to correspond to the data lines and the scanning lines on the substrate in plan view, and the pixel electrodes are electrically connected to the pixel-potential-side electrodes and the thin film transistors. This abstract is intended only to aid those searching patents, and is not intended to be used to interpret or limit the scope or meaning of the claims in any manner.

Abstract: An object of the invention is to manage variation of electrical characteristics of an element in a semiconductor device due to a vapor deposition process by measuring electrical characteristics of a TEG. A substrate 100 of an active matrix EL panel includes a vapor deposition region 101 having a film formed by a vapor deposition method. In the vapor deposition region 101, a pixel region 102 is provided. A TEG 109 is provided in the vapor deposition region 101 having a film formed in a vapor deposition step and outside of the pixel region 102. A measurement terminal portion 110 for measuring the TEG 109 is provided outside of a sealing region 103.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

Abstract: A method for forming a MIM-type capacitor by filling of trenches by conformal depositions of insulating materials and of conductive materials, two successive electrodes of the capacitor including on either side of a thin vertical insulating layer at least one conductive layer of same nature, including the step of lowering the level of the conductive layers with respect to the level of the insulating layer separating them.

Abstract: A light-emitting device includes a power feeding line to which a predetermined voltage is supplied; a light-emitting element formed of a first electrode, a second electrode, and a light-emitting layer interposed between the first electrode and the second electrode; and a driving transistor that controls the amount of current supplied to the light-emitting element from the power feeding line. The power feeding line includes a portion interposed between the first electrode and the driving transistor.

Abstract: This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

Abstract: A method for manufacture of application specific solar cells includes providing and processing custom design information to determine at least a cell size and a cell shape. The method includes providing a transparent substrate having a back surface region, a front surface region, and one or more grid-line regions overlying the front side surface region. The one or more grid regions provide one or more unit cells having the cell size and the cell shape. The method further includes forming a layered structure including photovoltaic materials overlying the front surface region.

Abstract: A thin film transistor (TFT) including a nanowire semiconductor layer having nanowires aligned in one direction in a channel region is disclosed. The nanowire semiconductor layer is selectively formed in the channel region. A method for fabricating the TFT, a liquid crystal display (LCD) device using the TFT, and a method for manufacturing the LCD device are also disclosed. The TFT fabricating method includes forming alignment electrodes on the insulating film such that the alignment electrodes face each other, to define a channel region, forming an organic film, to expose the channel region, coating a nanowire-dispersed solution on an entire surface of a substrate including the organic film, forming a nanowire semiconductor layer in the channel region by generating an electric field between the alignment electrodes such that nanowires of the nanowire semiconductor layer are aligned in a direction, and removing the organic film.

Abstract: A display substrate includes a base substrate having a display area and a peripheral area which surrounds the display area, a pixel electrode formed on the display area, a pad part formed on the peripheral area, an adhesion part formed on the peripheral area and having a plurality of holes formed in an area adjacent to the pad part on the peripheral area and a conductive adhesion member formed on the pad part and the adhesion part to make electrical contact with the pad part and a terminal of an integrated circuit.

Abstract: A light-emitting device comprises first and second dot members. The first dot member is formed so that it makes contact with the second dot member. The first dot member comprises a plurality of first quantum dot layers. Each of the plurality of first quantum dot layers comprises a plurality of first quantum dots and a silicon dioxide film. The first quantum dot comprises an n-type silicon dot. The second dot member comprises a plurality of second quantum dot layers. Each of the plurality of second quantum dot layers comprises a plurality of second quantum dots and a silicon dioxide film. The second quantum dot comprises a p-type silicon dot.

Abstract: A plurality of gate lines formed on an insulating substrate, each gate line including a pad for connection to an external device; a plurality of data lines intersecting the gate lines and insulated from the gate lines, each data line including a pad for connection to an external device; and a conductor overlapping at least one of the gate lines and the data lines are included. An overlapping distance of the gate lines or the data lines and a width of the conductor decreases as the length of the gate lines or the data lines increases. Accordingly, the difference in the RC delays due to the difference of the length of the signal lines is compensated to be reduced.

Abstract: A display device includes: a pixel array unit having pixels including a circuit configuration, in which a first electrode of an electro-optical element and a source electrode of a driving transistor are connected together, a gate electrode of the driving transistor and a source electrode or a drain electrode of a writing transistor are connected together, a holding capacitor is connected between the gate electrode and the source electrode of the driving transistor, and an auxiliary capacitor is connected between the first electrode and a second electrode of the electro-optical element, disposed on a substrate in a matrix shape, wherein, from one pixel of adjacent pixels to an area of the other pixel, the auxiliary capacitor of the one pixel is set to be disposed, and an electrode of the auxiliary capacitor that is disposed on the electro-optical element side is conductive with the second electrode of the electro-optical element.

Abstract: A fan-out unit which can control a resistance difference among channels with efficient space utilization and a thin-film transistor (TFT) array substrate having the fan-out unit are presented. The fan-out unit includes: an insulating substrate; a first wiring layer which is formed on the insulating substrate and connected to a pad; a second wiring layer which is formed on the insulating substrate and connected to a TFT; and a resistance controller which is connected between the first wiring layer and the second wiring layer and includes a plurality of first resistors extending parallel to the first wiring layer and a plurality of second resistors extending perpendicular to the first resistors and alternately connecting to the first resistors, wherein the first resistors are longer than the second resistors.

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The device includes: a substrate including a polymer build-up layer, and a passive structure embedded in the substrate. The passive structure includes a top conductive layer overlying the polymer build-up layer, a dielectric layer overlying the top conductive layer, and a bottom conductive layer overlying the dielectric layer. The device further includes a conductive via extending through the polymer build-up layer and electrically insulated from the bottom conductive layer, an insulation material insulating the conductive via from the bottom conductive layer, and a bridging interconnect disposed at a side of the top conductive layer facing away from the dielectric layer, the bridging interconnect electrically connecting the conductive via to the top conductive layer.

Abstract: A flat panel display capable of preventing inline short between adjacent wirings and voltage drop through power supply line by using pixel electrode layer as a power supply layer, and a fabrication method thereof. A flat panel display of the present invention is made up of a thin film transistor including source/drain electrodes, formed on an insulation substrate, an insulation film formed on the insulation substrate including the thin film transistor and including first and second contact holes for exposing the source/drain electrodes respectively, a pixel electrode formed on the insulation film and connected to one of the source/drain electrodes through one of the first and second contact holes, and a power supply layer formed on the insulation film and connected to the other one of the source/drain electrodes through the other one of the first and second contact holes.

Abstract: A display panel has a protection film having a recess. The recess is arranged above a storage electrode and corresponds to a location of the storage electrode in a plan view. A width of the recess is larger in plan view than a width of the storage electrode, and a pixel electrode is arranged on the protection film. The capacitance of a storage capacitor formed by charges stored in the pixel electrode and the storage electrode is determined by a thickness of the protection film and an overlapping area of the pixel electrode and the storage electrode.

Abstract: There is provided a writing circuit of an electro-optical device having a plurality of scanning lines, a plurality of data lines, and a plurality of pixels disposed to correspond to intersections between the plurality of scanning lines and the plurality of data lines. Here, each pixel comprises: a pixel capacitor having a pixel electrode and a common electrode opposed to the pixel electrode; and a switching element for electrically connecting the corresponding data line to the pixel electrode when the corresponding scanning line is selected. The writing circuit comprises an inversion circuit for maintaining a voltage between a potential of the data line and a predetermined potential for a predetermined time, and inverting the maintained voltage with respect to a reference potential and applying the inverted voltage to the data line after the lapse of the predetermined time, in a period of time when one scanning line of the plurality of scanning lines is selected.