Anti-blooming (epo) Patents (Class 257/E27.139)
  • Patent number: 8994139
    Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
  • Patent number: 8878266
    Abstract: A CMOS image sensor includes a substrate, a gate electrode formed over the substrate, a photodiode formed over the substrate to be substantially aligned with one side of the gate electrode, a floating diffusion region formed over the substrate to be substantially aligned with the other side of the gate electrode, and a blooming pass region formed below the photodiode.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Youn-Sub Lim
  • Patent number: 8643064
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Publication number: 20140008708
    Abstract: A CMOS image sensor includes a substrate, a gate electrode formed over the substrate, a photodiode formed over the substrate to be substantially aligned with one side of the gate electrode, a floating diffusion region formed over the substrate to be substantially aligned with the other side of the gate electrode, and a blooming pass region formed below the photodiode.
    Type: Application
    Filed: August 30, 2012
    Publication date: January 9, 2014
    Inventor: Youn-Sub LIM
  • Patent number: 8624277
    Abstract: A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: January 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Min Kim, Bo-Sung Kim, Seon-Pil Jang, Seung-Hwan Cho, Kang-Moon Jo
  • Patent number: 8558286
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 15, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8546853
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: October 1, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530992
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530940
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530991
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530993
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8525287
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 3, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8513758
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: August 20, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8482093
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: July 9, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8476727
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 2, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8471351
    Abstract: Each of pixels 10 arranged in an array pattern includes a photoelectric conversion element 11, a transfer transistor 13 for transferring charges to a floating diffusion layer 12, and an amplifier transistor 14 for outputting the transferred charges to an output line. An insulating isolation part 22 isolates the adjacent photoelectric conversion elements 11, and isolates the photoelectric conversion element 11 and the amplifier transistor 14. The insulating isolation part 22 constitutes a first region A between the photoelectric conversion elements 11 where the amplifier transistor 14 is not arranged, and a second region B between the photoelectric conversion elements 11 where the amplifier transistor 14 is arranged. First and second isolation diffusion layers 23 and 24 are formed below the insulating isolation part 22, and the second isolation diffusion layer 24 is wider than the first isolation diffusion layer 23 in the first region A.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Yusuke Otake, Hitomi Fujiwara
  • Patent number: 8466533
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: June 18, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8441090
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 14, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8395194
    Abstract: A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Haruhisa Yokoyama, Hiroshi Sakoh, Kazuhiro Yamashita, Mitsuo Yasuhira, Yuichi Hirofuji
  • Patent number: 8378401
    Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
  • Patent number: 8329499
    Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: December 11, 2012
    Assignee: Truesense Imaging, Inc.
    Inventors: Edmund K. Banghart, Eric G. Stevens, Hung Q. Doan
  • Patent number: 8274126
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: September 25, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8269302
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 18, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8269260
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 18, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8203195
    Abstract: Optically sensitive devices include a device comprising a first contact and a second contact, each having a work function, and an optically sensitive material between the first contact and the second contact. The optically sensitive material comprises a p-type semiconductor, and the optically sensitive material has a work function. Circuitry applies a bias voltage between the first contact and the second contact. The optically sensitive material has an electron lifetime that is greater than the electron transit time from the first contact to the second contact when the bias is applied between the first contact and the second contact. The first contact provides injection of electrons and blocking the extraction of holes. The interface between the first contact and the optically sensitive material provides a surface recombination velocity less than 1 cm/s.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: June 19, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Igor Constantin Ivanov, Edward Hartley Sargent, Hui Tian
  • Patent number: 8188519
    Abstract: A solid-state imaging device that includes: a pixel array section configured by an array of a unit pixel, including an optoelectronic conversion section that subjects an incoming light to optoelectronic conversion and stores therein a signal charge, a transfer transistor that transfers the signal charge stored in the optoelectronic conversion section, a charge-voltage conversion section that converts the signal charge provided by the transfer transistor into a signal voltage, and a reset transistor that resets a potential of the charge-voltage conversion section; and voltage setting means for setting a voltage of a well of the charge-voltage conversion section to be negative.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventor: Fumihiko Koga
  • Publication number: 20120104464
    Abstract: A CMOS image sensor is disclosed. The CMOS image sensor includes a semiconductor substrate having a surface. An epitaxial layer is grown on the surface. A p-type CMOS pixel formed substantially in the epitaxial layer. In one version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at a predetermined distance from the surface and which decreases monotonically on both sides of the profile from the maximum value within the semiconductor substrate and the epitaxial layer. In another version of the CMOS image sensor, there exists a net n-type dopant concentration profile in the semiconductor substrate and the epitaxial layer which has a maximum value at the surface and which decreases monotonically with increasing distance from the surface within the semiconductor substrate and the epitaxial layer.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 3, 2012
    Inventors: James Robert Janesick, Peter Alan Levine, John Robertson Tower
  • Patent number: 8106431
    Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: January 31, 2012
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
  • Patent number: 8105864
    Abstract: Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration, a second pixel cell having a second configuration, and at least one barrier region formed between the first and second pixel cells for capturing and removing charge. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: January 31, 2012
    Assignee: Aptina Imaging Corporation
    Inventors: Howard E. Rhodes, Richard A. Mauritzson, William T. Quinlin
  • Patent number: 8097908
    Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: January 17, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Chen Xu, Gennadiy Agranov, Igor Karasev
  • Patent number: 8084796
    Abstract: A solid state imaging apparatus includes: a plurality of photoelectric conversion cells each including a plurality of photoelectric sections arranged in an array of at least two rows and two columns; a plurality of floating diffusion sections each being connected to each of ones of the photoelectric sections which are included in the same row of each said photoelectric conversion cell via each of a plurality of transfer transistors, and being shared by said ones of the photoelectric sections; a plurality of read-out lines each being selectively connected to at least two of the transfer transistors; and a plurality of pixel amplifier transistors each detecting and outputting the potential of each said the floating diffusion section. Charges of the photoelectric conversion sections each being connected to one of the read-out lines and being read out by the transfer transistors are read out by different floating diffusion sections.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: December 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Takumi Yamaguchi, Takahiko Murata
  • Patent number: 8013412
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 6, 2011
    Assignee: InVisage Technologies, Inc.
    Inventor: Hui Tian
  • Patent number: 8004057
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: August 23, 2011
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Publication number: 20110187909
    Abstract: Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region.
    Type: Application
    Filed: August 2, 2010
    Publication date: August 4, 2011
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Hong Zhu, Jianping Yang
  • Patent number: 7923801
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: April 12, 2011
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Hartley Sargent
  • Patent number: 7902624
    Abstract: Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration, a second pixel cell having a second configuration, and at least one barrier region formed between the first and second pixel cells for capturing and removing charge. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: March 8, 2011
    Assignee: Aptina Imaging Corporation
    Inventors: Howard E. Rhodes, Richard A. Mauritzson, William T. Quinlin
  • Patent number: 7777229
    Abstract: A method for fabricating a back-illuminated semiconductor imaging device and resulting imaging device is disclosed, which includes the steps providing a substrate having a front surface and a back surface; growing an epitaxial layer substantially overlying the front surface of the substrate; forming at least one barrier layer substantially within the epitaxial layer; fabricating at least one imaging structure overlying and extending into the epitaxial layer, the imaging structure at least one charge transfer region, the at least one barrier layer substantially underlying the at least one charge transfer region, wherein light incident on the back surface of the substrate generates charge carriers which are diverted away from the at least one charge transfer region by the at least one barrier layer. At least a portion of the epitaxial layer is grown using an epitaxial lateral overgrowth technique.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 17, 2010
    Assignee: Sarnoff Corporation
    Inventors: Pradyumna Kumar Swain, Mahalingam Bhaskaran, Peter Levine, Norman Goldsmith
  • Publication number: 20100163933
    Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.
    Type: Application
    Filed: March 8, 2010
    Publication date: July 1, 2010
    Inventors: Chen Xu, Gennadiy Agranov, Igor Karasev
  • Patent number: 7718460
    Abstract: A method for manufacturing a solid state imaging device includes steps of forming a photodiode layer buried in a semiconductor substrate by ion injection and of forming a shielding layer buried in the photodiode layer by ion injection. At least in the ion injection process in the step of forming the shielding layer, an ion injection pause period is provided at least one time during whole ion injection step. According to the method, crystal defects are prevented from generating even if ion injection is performed with high energy, thereby suppressing dark current without complexity in manufacturing process.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 18, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shu Sasaki
  • Patent number: 7595519
    Abstract: An image sensor includes a first type semiconductor layer, a second type semiconductor layer and a first type well. The first type semiconductor layer is formed on a semiconductor substrate and includes a plurality of pixels which receive external light and convert optical charges into an electrical signal. The second type semiconductor layer is supplied with a drain voltage to have a potential different from that of the first semiconductor layer, and the first type well controls a power source voltage (VDD) using the drain voltage.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: September 29, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Jin Lee, Yo-Han Sun, Tae-Seok Oh, Sung-Jae Joo, Bum-Suk Kim, Yun-Ho Jang, Sae-Young Kim, Keun-Chan Yuk
  • Patent number: 7557390
    Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: July 7, 2009
    Assignee: Sanyo Electric co., Ltd.
    Inventors: Yoshihiro Okada, Yuzo Otsuru
  • Patent number: 7459735
    Abstract: A solid-state imaging device capable of reducing the occurrence of a dark current and a pixel defect is provided. A solid-state imaging device 10 is formed in which a plurality of photoelectric conversion elements 4 are formed in a semiconductor substrate 1; circuits 5 which read out signal charge from each of the plurality of photoelectric conversion elements 4 are respectively formed on the semiconductor substrate 1; light is applied from the opposite side to the circuits 5 which read out signal charge from each of the plurality of photoelectric conversion elements; and a gettering region is provided in an element-isolation area 2 which separate the photoelectric conversion elements 4 adjacent to each other.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: December 2, 2008
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama, Hideo Kanbe
  • Patent number: 7385272
    Abstract: An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: June 10, 2008
    Assignee: ESS Technology, Inc.
    Inventors: Zeynep Toros, Richard Mann, Selim Bencuya
  • Patent number: 7378691
    Abstract: A solid-state image sensor capable of suppressing blooming and increase of a dark current also when an n-type impurity concentration in a transfer channel region is increased is obtained. In this solid-state image sensor, gate electrodes of a prescribed pixel and another pixel adjacent to the prescribed pixel are provided at a first space, and a larger quantity of second conductivity type impurity is introduced into a region of a first conductivity type transfer channel region, located on the main surface of a substrate, corresponding to the first space as compared with a second conductivity type impurity contained in the remaining region of the transfer channel region other than the region corresponding to the first space.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 27, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tatsurou Geshi, Mamoru Arimoto
  • Patent number: 7279770
    Abstract: A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first portion. The first width is greater than the second width. A first insulating liner is formed along at least lateral sidewalls of the first portion. A spacer material is formed along at least lateral sidewalls of the insulating liner and filling the second portion. A filler material is over said spacer material and within the first portion. Methods for forming the structure are also provided.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 7239003
    Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: July 3, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Chandra Mouli, Howard Rhodes
  • Patent number: RE44482
    Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight A CMOS active pixel image sensor includes a plurality of pinned photodiode photodetectors that use a common output transistor. In one configuration, the charge from two or more pinned photodiodes may be binned together and applied to the gate of an output transistor.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: September 10, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Vladimir Berezin, Alexander I. Krymski, Eric R. Fossum