Abstract: A medical system including a medical imaging device, and circuitry that obtains a plurality of first images each having a different phase from the medical imaging device, combines each of the plurality of first images a plurality of times to generate a plurality of second images, wherein each time of the plurality of times that the plurality of first images are combined, a different candidate process is used in the combining, and selects one image from the plurality of second images as an output image for display, the selected one image being higher quality than any one of the plurality of first images.

Abstract: A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.

Abstract: An image sensor includes a plurality of non-color pixel sensors each configured to sense a non-color signal; and a color pixel sensing region including at least one color pixel sensor configured to sense a color signal, wherein the color pixel sensing region has an area physically greater than an area of each of the non-color pixel sensors.

Abstract: An apparatus for imaging an object has an image sensor that comprises a plurality of pixels. The plurality of pixels is matrix-arrayed along vertical and horizontal directions. The apparatus also has an image sensor driver that drives the image sensor, and the image sensor driver is capable of reading image-pixel signals of neighboring pixels among the plurality of pixels while mixing the image-pixel signals. The apparatus also has a pixel addition setting processor that sets the number of pixel addition with respect to at least one of at least one row and at least one column. The pixel addition setting processor sets different numbers of pixel addition to different pixel areas. The image sensor driver reads the image-pixel signals in response to the set number of pixel addition.

Abstract: A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter comprising a first material layer and a second material layer formed in association with the first shaping material layer.

Abstract: Provided is a solid-state image sensor, including: a pixel unit including a valid pixel area and an optical-black pixel area; a plurality of reading units configured to read pixel values of a large number of pixels of the pixel unit line by line; a plurality of correction data generating units corresponding to the plurality of reading units, respectively, each of the plurality of correction data generating units being configured to generate correction data based on pixel values read from the optical-black pixel area out of the pixel values read from the pixel unit by the corresponding reading unit line by line; and a correcting unit configured to correct pixel values read from the valid pixel area out of the pixel values read from the pixel unit by the reading unit line by line based on the correction data generated by the corresponding correction data generating unit.

Abstract: In various embodiments, image sensors include strapping grids of vertical and horizontal strapping lines conducting phase-control signals to underlying gate conductors that control transfer of charge within the image sensor.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.

Abstract: A method for manufacturing a solid-state imaging device in which a charge generator that detects an electromagnetic wave and generates signal charges is formed on a semiconductor substrate and a negative-charge accumulated layer having negative fixed charges is formed above a detection plane of the charge generator. The method includes the steps of: forming an oxygen-feed film capable of feeding oxygen on the detection plane of the charge generator; forming a metal film that covers the oxygen-feed film on the detection plane of the charge generator; and performing heat treatment for the metal film in an inactive atmosphere to thereby form an oxide of the metal film between the metal film and the oxygen-feed film on the detection plane of the charge generator, the oxide being to serve as the negative-charge accumulated layer.

Abstract: The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

Abstract: A floating diffusion (331) is created substantially at center of the light-receiving surface of an embedded photodiode (31), with a gate electrode of a transfer transistor (32) surrounding the floating diffusion. The concentration (or depth) of impurities in a p+-type semiconductor region, n-type semiconductor region or p-well region is changed in an inclined form so that a potential gradient being inclined downwards from the circumference to the center is created when an appropriate bias voltage is applied to the pn junction. The photocharges produced by incident light are rapidly moved along the potential gradient toward the center. Even in the case where the photocharge storage time is short, the photocharges can be efficiently collected since the maximum moving distance from the circumference of the photodiode (31) to the floating diffusion (331). Thus, the photocharges produced by the photodiode (31) are efficiently utilized, whereby the detection sensitivity is improved.

Abstract: Ultraviolet or Extreme Ultraviolet and/or visible detector apparatus and fabrication processes are presented, in which the detector includes a thin graphene electrode structure disposed over a semiconductor surface to provide establish a potential in the semiconductor material surface and to collect photogenerated carriers, with a first contact providing a top side or bottom side connection for the semiconductor structure and a second contact for connection to the graphene layer.

Abstract: In various embodiments, image sensors include strapping grids of vertical and horizontal strapping lines conducting phase-control signals to underlying gate conductors that control transfer of charge within the image sensor.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of less than about 0.4 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.

Abstract: The present invention provides a junction gate photo-diode (JGP) pixel that includes a JGP accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also includes is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also includes is a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD. The PB temporarily blocks charge transfer between the JGP and the FD, and the SG stores the accumulated charge from the JGP, and transfers the stored charge to the FD for readout.

Abstract: A solid-state imaging device including: light-receiving units which are formed in rows and columns; a transfer channel formed in each column; first and second transfer electrodes that are formed in the same layer and deposited alternately above the transfer channel; insulating regions each formed above the transfer channel and between one of the first transfer electrodes and one of the second transfer electrodes which are adjacent to each other; an antireflection film formed above the light-receiving units, and formed on the insulating regions to cover the insulating regions; a first wire formed in each row in a layer upper than the antireflection film, and electrically connected to second transfer electrodes; and a light-shielding film which is formed in a layer upper than the first wire, covers the transfer channel, and has an opening above each of the light-receiving units.

Abstract: Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.

Abstract: According to one embodiment, a solid-state imaging device including a plurality of pixels two-dimensionally arranged at a preset pitch in a semiconductor substrate is provided. Each of the pixels is configured to include first and second photodiodes that photoelectrically convert incident light and store signal charges obtained by conversion, a first micro-lens that focuses light on the first photodiode, and a second micro-lens that focuses light on the second photodiode. The saturation charge amount of the second photodiode is larger than that of the first photodiode. Further, the aperture of the second micro-lens is smaller than that of the first micro-lens.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating film formed on a transfer electrode and having a negative fixed charge.

Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: A photoelectric conversion device including: a first electrode; a photoelectric conversion layer; and a second electrode, in this order, wherein the photoelectric conversion device further includes: a deterioration factor adsorptive and/or reactive layer which covers the first electrode, the photoelectric conversion layer and the second electrode and which has at least one of adsorptivity of adsorbing a deterioration factor and reactivity of reacting with the deterioration factor; and a passivation layer which covers the deterioration factor adsorptive and/or reactive layer to protect the first electrode, the photoelectric conversion layer and the second electrode.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: A method of manufacturing a solid-state imaging device, wherein the solid-state imaging device comprising: a semiconductor substrate; a plurality of photodiodes that are formed on a surface of the semiconductor substrate so as to be arranged in an array form; and a light shielding film, provided on or above the surface of the semiconductor substrate, that has a plurality of openings in correspondence with respective ones of the photodiodes, the method comprising: laminating, on the surface of the semiconductor substrate, lamination layers including the light shielding film; opening through holes in the lamination layers, respectively, at positions corresponding to the photodiodes to form the openings in the light shielding film; forming a low refractive index material layer with a predetermined thickness isotropically on a side wall surface of each of the through holes; and filling a remaining hole portion of each of the through holes with a high refractive index material to form an optical waveguide for guid

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Abstract: A solid-state image pick-up device of a photoelectric converting film lamination type including a semiconductor substrate and at least three layers of photoelectric converting films each of which is interposed between a common electrode film and pixel electrode films. The pixel electrode films correspond to pixels respectively, and at least three layers of photoelectric converting films are laminated through insulating layers. The at least three layers of photoelectric converting films are above the semiconductor substrate. Sets of the pixel electrode films are provided on each of the at least three layers of photoelectric converting films, and electric charge storage portions formed on the semiconductor substrate are connected through sets of columnar contact electrodes. Resistance values of the sets of columnar contact electrodes are equal to each other.