With Specified Crystalline Planes Or Axis (epo) Patents (Class 257/E29.004)
  • Patent number: 10141401
    Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Patent number: 9666668
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Patent number: 9559090
    Abstract: A silicon wafer includes a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein the plurality of chip patterns include one or more patterns arranged in the first direction and the second direction in a straight line, the plurality of chip patterns include a first chip pattern and a second chip pattern adjacent to the first chip pattern, and the second chip pattern is arranged by rotating the first chip pattern at 90 degrees, the plurality of chip patterns are arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different, and an angle between the axis and the first direction of the second chip pattern is 90 degrees.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: January 31, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Tatsuro Takagaki
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8936993
    Abstract: A hybrid substrate comprises first and second active areas made from semiconductor materials laterally offset from one another and separated by an isolation area. The main surfaces of the isolation area and of the first active area form a plane. The hybrid substrate is obtained from a source substrate successively comprising layers made from a first and second semiconductor materials separated by an isolation layer. A single etching mask is used to pattern the isolation area, first active area and second active area. The main surface of the first active area is released thereby forming voids in the source substrate. The etching mask is eliminated above the first active area. A first isolation material is deposited, planarized and etched until the main surface of the first active area is released.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 20, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Claire Fenouillet-Béranger, Stéphane Denorme, Philippe Coronel
  • Patent number: 8933543
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8921858
    Abstract: In a light-emitting device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hidekazu Miyairi
  • Patent number: 8907359
    Abstract: An optoelectronic semiconductor component comprising a semiconductor layer sequence (3) based on a nitride compound semiconductor and containing an n-doped region (4), a p-doped region (8) and an active zone (5) arranged between the n-doped region (4) and the p-doped region (8) is specified. The p-doped region (8) comprises a p-type contact layer (7) composed of InxAlyGa1-x-yN where 0?x?1, 0?y?1 and x+y?1. The p-type contact layer (7) adjoins a connection layer (9) composed of a metal, a metal alloy or a transparent conductive oxide, wherein the p-type contact layer (7) has first domains (1) having a Ga-face orientation and second domains (2) having an N-face orientation at an interface with the connection layer (9).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Strassburg, Lutz Höppel, Matthias Peter, Ulrich Zehnder, Tetsuya Taki, Andreas Leber, Rainer Butendeich, Thomas Bauer
  • Patent number: 8889531
    Abstract: A semiconductor body comprised of a semiconductor material includes a first monocrystalline region of the semiconductor material having a first lattice constant along a reference direction, a second monocrystalline region of the semiconductor material having a second lattice constant, which is different than the first, along the reference direction, and a third, strained monocrystalline region between the first region and the second region.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Reinhart Job
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8878345
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 4, 2014
    Assignee: AETech Corporation
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8866204
    Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 21, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Qing Liu, Junli Wang
  • Patent number: 8829658
    Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi Arakawa, Michimasa Miyanaga, Takashi Sakurada, Yoshiyuki Yamamoto, Hideaki Nakahata
  • Patent number: 8823014
    Abstract: A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 2, 2014
    Assignees: Kansas State University Research Foundation, State University of New York Stony Brook, The University of Bristol
    Inventors: James Edgar, Michael Dudley, Martin Kuball, Yi Zhang, Guan Wang, Hui Chen, Yu Zhang
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8810009
    Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semiconductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 19, 2014
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Seth A. Fortuna
  • Patent number: 8779437
    Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8772779
    Abstract: A display substrate includes a driving element, a switching element, a gate line, a data line, a driving voltage line and an electroluminescent element. The driving element includes a driving control electrode formed from a first conductive layer, and a driving input electrode and a driving output electrode formed from a second conductive layer. The switching element includes a switching control electrode formed from the second conductive layer, and a switching input electrode and a switching output electrode formed from a third conductive layer. The gate and data lines are formed from the second and third conductive layers, respectively. The driving voltage line is formed from the third conductive layer. Thus, misalignment between upper and lower patterns may be prevented to improve the reliability of a manufacturing process and increase an aperture ratio, thereby enhancing display quality.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: July 8, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Chul Jung, Baek-Woon Lee, Joon-Chul Goh
  • Patent number: 8723233
    Abstract: An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation. The single-crystal fin having the first crystal orientation and the single-crystal fin having the second crystal orientation are substantially parallel.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Katherine L. Saenger
  • Patent number: 8710555
    Abstract: In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang, Junga Choi
  • Patent number: 8709925
    Abstract: A method of controlled p-type conductivity in (Al,In,Ga,B)N semiconductor crystals. Examples include {10 11} GaN films deposited on {100} MgAl2O4 spinel substrate miscut in the <011> direction. Mg atoms may be intentionally incorporated in the growing semipolar nitride thin film to introduce available electronic states in the band structure of the semiconductor crystal, resulting in p-type conductivity. Other impurity atoms, such as Zn or C, which result in a similar introduction of suitable electronic states, may also be used.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: April 29, 2014
    Assignee: The Regents of the University of California
    Inventors: John F. Kaeding, Hitoshi Sato, Michael Iza, Hirokuni Asamizu, Hong Zhong, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8704340
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8704273
    Abstract: A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Atsushi Yamada
  • Patent number: 8674451
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: March 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Simon Su-Horng Lin, Chi-Ming Yang, Chyi-Shyuan Chern, Chin-Hsiang Lin
  • Patent number: 8629446
    Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8618639
    Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8610181
    Abstract: A structure includes a substrate containing at least first and second adjacent gate structures on a silicon surface of the substrate and a silicided source/drain region formed in a V-shaped groove between the first and second adjacent gate structures. The silicided source/drain region formed in the V-shaped groove extend substantially from an edge of the first gate structure to an opposing edge of the second gate structure.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8604524
    Abstract: The present invention facilitates semiconductor device fabrication and performance by providing a semiconductor device that can improve channel mobility for both N type and P type transistor devices. The semiconductor device of the present invention is fabricated on a semiconductor substrate 802 that has a first and second crystallographic orientation axes (e.g., <110>, <100>) 804 and 806. Source to drain channel regions for P type devices are formed 904 and aligned along the first crystallographic orientation axis. Source to drain channel regions for N type devices are formed 906 rotated from the channel regions of the P type devices by an offset angle so that the source to drain channel regions for the N type devices are aligned with the second crystallographic orientation axis.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Timothy A Rost
  • Patent number: 8574969
    Abstract: An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: November 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Katherine L. Saenger
  • Patent number: 8536030
    Abstract: A method of manufacturing a semipolar semiconductor crystal comprising a group-III-nitride (III-N), the method comprising: providing a substrate comprising sapphire (Al2O3) having a first surface that intersects c-planes of the sapphire; forming a plurality of trenches in the first surface, each trench having a wall whose surface is substantially parallel to a c-plane of the substrate; epitaxially growing a group-III-nitride (III-N) material in the trenches on the c-plane surfaces of their walls until the material overgrows the trenches to form a second planar surface, substantially parallel to a (20-2l) crystallographic plane of the group-III-nitride, wherein l is an integer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 17, 2013
    Assignee: Freiberger Compund Materials GmbH
    Inventors: Thomas Wunderer, Stephan Schwaiger, Ilona Argut, Rudolph Rosch, Frank Lipski, Ferdinand Scholz
  • Patent number: 8531010
    Abstract: A semiconductor structure may include, but is not limited to: a semiconductor substrate; a first semiconductor structure extending upwardly over the semiconductor substrate; and a second semiconductor structure extending upwardly over the semiconductor substrate, the first and second semiconductor structures being aligned in a first <100> direction.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Kiyonori Oyu, Kazuhiro Nojima
  • Patent number: 8507365
    Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a?) that is related to the substrate lattice parameter (a). The lattice parameter (a?) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 13, 2013
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak
  • Patent number: 8507921
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 13, 2013
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8482041
    Abstract: In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: July 9, 2013
    Assignee: Unisantis Electronics Singapore Pte Ltd.
    Inventors: Fujio Masuoka, Keon Jae Lee
  • Patent number: 8435880
    Abstract: In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than ?0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: May 7, 2013
    Assignee: Sony Corporation
    Inventors: Akira Ohmae, Kota Tokuda, Masayuki Arimochi, Nobuhiro Suzuki, Michinori Shiomi, Tomonori Hino, Katsunori Yanashima
  • Publication number: 20130082262
    Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.
    Type: Application
    Filed: September 25, 2012
    Publication date: April 4, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: SEMICONDUCTOR ENERGY LABORATORY CO.
  • Publication number: 20130082360
    Abstract: A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.
    Type: Application
    Filed: July 18, 2012
    Publication date: April 4, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Toyoo MIYAJIMA, Kenji IMANISHI, Atsushi YAMADA, Norikazu NAKAMURA
  • Publication number: 20130082357
    Abstract: A base layer of a semiconductor material is formed with a naturally textured surface. The base layer may be incorporated within a photovoltaic structure. A controlled spalling technique, in which substrate fracture is propagated in a selected direction to cause the formation of facets, is employed. Spalling in the [110] directions of a (001) silicon substrate results in the formation of such facets of the resulting base layer, providing a natural surface texture.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ibrahim Alhomoudi, Stephen W. Bedell, Keith E. Fogel, Paul A. Lauro, Ning Li, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8399915
    Abstract: Provided is a semiconductor device which can reduce on-resistance by improving hole mobility of a channel region. A trench gate type MOSFET (semiconductor device) is provided with a p+-type silicon substrate whose crystal plane of a main surface is a (110) plane; an epitaxial layer formed on the silicon substrate; a trench, which is formed on the epitaxial layer and includes a side wall parallel to the thickness direction (Z direction) of the silicon substrate; a gate electrode formed inside the trench through a gate dielectric film; an n-type channel region formed along the side wall of the trench; and a p+-type source region and a p?-type drain region which are formed to sandwich the channel region in the thickness direction (Z direction) of the silicon substrate. The trench is formed to have the crystal plane of the side wall as a (110) plane.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: March 19, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Publication number: 20130064261
    Abstract: An edge emitting solid state laser and method. The laser comprises at least one AlInGaN active layer on a bulk GaN substrate with a non-polar or semi-polar orientation. The edges of the laser comprise {1 1?2±6} facets. The laser has high gain, low threshold currents, capability for extended operation at high current densities, and can be manufactured with improved yield. The laser is useful for optical data storage, projection displays, and as a source for general illumination.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 14, 2013
    Applicant: Soraa, Inc.
    Inventors: Rajat Sharma, Eric M. Hall, Christiane Poblenz, Mark P. D'Evelyn
  • Publication number: 20130062738
    Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation <111> is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.
    Type: Application
    Filed: May 29, 2012
    Publication date: March 14, 2013
    Inventor: Chung-Nan Chen
  • Publication number: 20130062739
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Application
    Filed: February 8, 2011
    Publication date: March 14, 2013
    Applicant: Takafumi YAO
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8395218
    Abstract: The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: March 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Dong-Won Kim, Kyoung-Hwan Yeo
  • Patent number: 8394681
    Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: March 12, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Ashesh Parikh, Anand Seshadri
  • Patent number: 8384196
    Abstract: Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, James Fiorenza, Jennifer M. Hydrick, Anthony J. Lochtefeld, Ji-Soo Park, Jie Bai, Jizhong Li
  • Publication number: 20130037920
    Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.
    Type: Application
    Filed: April 28, 2011
    Publication date: February 14, 2013
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Yutaka Shiga, Hiroshi Takeno
  • Publication number: 20130026482
    Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.
    Type: Application
    Filed: July 29, 2011
    Publication date: January 31, 2013
    Applicant: Bridgelux, Inc.
    Inventor: William E. Fenwick
  • Publication number: 20130026607
    Abstract: A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in manufacturing the line of material.
    Type: Application
    Filed: July 25, 2011
    Publication date: January 31, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Victor Moroz, Lars Bomholt
  • Patent number: 8362575
    Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin