With Specified Crystalline Planes Or Axis (epo) Patents (Class 257/E29.004)
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Patent number: 8053776Abstract: In a vertical diode, an N+-type layer, an N?-type layer, and a P+-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N?-type layer is lower than the effective impurity concentrations of the N+-type layer and the P+-type layer. At least one of the N+-type layer, the N?-type layer, and the P+-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.Type: GrantFiled: November 12, 2009Date of Patent: November 8, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takuo Ohashi
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Patent number: 8053844Abstract: Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices on the first areas and second type devices on the second areas, wherein the first type devices are parallel or perpendicular to the second type devices. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).Type: GrantFiled: April 28, 2009Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventor: Dureseti Chidambarrao
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Publication number: 20110266550Abstract: This invention provides a method of forming semiconductor films on dielectrics at temperatures below 400° C. Semiconductor films are required for thin film transistors (TFTs), on-chip sensors, on-chip micro-electromechanical systems (MEMS) and monolithic 3D-integrated circuits. For these applications, it is advantageous to form the semiconductor films below 400° C. because higher temperatures are likely to destroy any underlying devices and/or substrates. This invention successfully achieves low temperature growth of germanium films using diboran. First, diboran gas is supplied into a reaction chamber at a temperature below 400° C. The diboran decomposes itself at the given temperature and decomposed boron is attached to the surface of a dielectric, for e.g., SiO2, forming a nucleation site and/or a seed layer. Second, source gases for semiconductor film formation, for e.g., SiH4, GeH4, etc., are supplied into the chamber, thereby forming a semiconductor film.Type: ApplicationFiled: May 17, 2011Publication date: November 3, 2011Applicants: STANFORD UNIVERSITY, NEC CORPORATIONInventors: Munehiro TADA, Krishna SARASWAT
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Publication number: 20110254058Abstract: A GAA (Gate-All-Around) CMOSFET device includes a semiconductor substrate, a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The surfaces of the first channel and the second channel are substantially surrounded by the gate region. A buried insulation layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the semiconductor substrate to isolate them from one another. The structure is simple, compact and highly integrated, has high carrier mobility, and avoids polysilicon gate depletion and short channel effect.Type: ApplicationFiled: February 11, 2010Publication date: October 20, 2011Applicant: Shanghai Institute of Microsystem and Information Technology Chinese AcademyInventors: Deyuan Xiao, Xi Wang
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Patent number: 8039877Abstract: A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer.Type: GrantFiled: September 9, 2008Date of Patent: October 18, 2011Assignee: Fairchild Semiconductor CorporationInventors: Tat Ngai, Qi Wang
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Patent number: 8039878Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.Type: GrantFiled: June 23, 2010Date of Patent: October 18, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
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Publication number: 20110233689Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.Type: ApplicationFiled: November 27, 2009Publication date: September 29, 2011Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE FOR MATERIALS SCIENCEInventors: Masahiko Hata, Noboru Fukuhara, Hisashi Yamada, Shinichi Takagi, Masakazu Sugiyama, Mitsuru Takenaka, Tetsuji Yasuda, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii, Akihiro Ohtake, Jun Nara
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Publication number: 20110227198Abstract: A method of manufacturing a semipolar semiconductor crystal comprising a group-III-nitride (III-N), the method comprising: providing a substrate comprising sapphire (Al2O3) having a first surface that intersects c-planes of the sapphire; forming a plurality of trenches in the first surface, each trench having a wall whose surface is substantially parallel to a c-plane of the substrate; epitaxially growing a group-III-nitride (III-N) material in the trenches on the c-plane surfaces of their walls until the material overgrows the trenches to form a second planar surface, substantially parallel to a (20-2l) crystallographic plane of the group-III-nitride, wherein l is an integer.Type: ApplicationFiled: March 18, 2011Publication date: September 22, 2011Applicant: FREIBERGER COMPOUND MATERIALS GMBHInventors: Thomas WUNDERER, Stephan SCHWAIGER, Ilona ARGUT, Rudolph ROSCH, Frank LIPSKI, Ferdinand SCHOLZ
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Publication number: 20110220915Abstract: A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.Type: ApplicationFiled: December 13, 2010Publication date: September 15, 2011Inventors: James Edgar, Michael Dudley, Martin Kuball, Yi Zhang, Guan Wang, Hui Chen, Yu Zhang
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Patent number: 8013320Abstract: A nitride semiconductor device includes a semiconductor stacked structure which is formed of a nitride semiconductor having a first principal surface and a second principal surface opposed to the first principal surface and which includes an active layer. The first principal surface of the semiconductor stacked structure is formed with a plurality of indentations whose plane orientations are the {0001} plane, and the plane orientation of the second principal surface is the {1-101} plane. The active layer is formed along the {1-101} plane.Type: GrantFiled: March 1, 2007Date of Patent: September 6, 2011Assignee: Panasonic CorporationInventors: Hisayoshi Matsuo, Tatsuo Morita, Tetsuzo Ueda, Daisuke Ueda
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Patent number: 8008692Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.Type: GrantFiled: September 18, 2008Date of Patent: August 30, 2011Assignee: EON Silicon Solution Inc.Inventors: Hung-Wei Chen, Yider Wu
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Publication number: 20110198560Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.Type: ApplicationFiled: February 13, 2009Publication date: August 18, 2011Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
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Publication number: 20110193201Abstract: The present invention notably concerns a method to fabricate and treat a structure of semiconductor-on-insulator type, successively comprising a carrier substrate (1), an oxide layer (3) and a thin layer (2) of semiconducting material, according to which: 1) a mask is formed on said thin layer (2) so as to define exposed regions (20), on the surface of said layer, which are not covered by the mask; 2) heat treatment is applied so as to urge at least part of the oxygen of the oxide layer (3) to diffuse through the thin layer (2), leading to controlled removal of the oxide in the regions (30) of the oxide layer (3) corresponding to the desired pattern; characterized in that said carrier substrate (1) and thin layer (2) are arranged relative to each other so that their crystal lattices, in a plane parallel to their interface (I), together form an angle called a “twist angle” of no more than 1°, and in a plane perpendicular to their interface (I) an angle called a “tilt angle” of no more than 1°, and in that a thType: ApplicationFiled: October 9, 2009Publication date: August 11, 2011Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Oleg Kononchuk, Eric Guiot, Fabrice Gritti, Didier Landru, Christelle Veytizou
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Patent number: 7993990Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: April 9, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Publication number: 20110180806Abstract: A structure and method for a semiconductor device includes a silicon device layer and a gallium nitride (GaN) device layer. In an embodiment, the silicon device layer and the GaN device layer have upper surfaces which are coplanar with each other. In another embodiment, the GaN device layer does not directly underlie the silicon device layer, and the silicon device layer does not directly underlie the GaN device layer. The semiconductor device can further include a silicon-based semiconductor device formed on and/or within the silicon device layer, and a nitride-based semiconductor device formed on and/or within the GaN device layer. The GaN device layer can include a plurality of layers which can be formed as conformal blanket layers and then planarized, or which can be selectively formed then planarized.Type: ApplicationFiled: November 15, 2010Publication date: July 28, 2011Inventor: Francois Hebert
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Publication number: 20110180857Abstract: A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicant: Raytheon CompanyInventors: William E. Hoke, Jeffrey R. LaRoche
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Patent number: 7985990Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.Type: GrantFiled: August 11, 2009Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Ashesh Parikh, Anand Seshadri
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Publication number: 20110175099Abstract: Methods and devices are described relating to an electronic device positioned at a known location in a crystalline film including a crystalline semiconductor comprising a region of location controlled crystalline grains; a device located in the crystalline semiconductor film at a location that is defined relative to the location of the location controlled crystalline grains. The method includes irradiating at least a portion of a semiconductor film using two or more overlapping irradiation steps, wherein each irradiation step at least partially melts and laterally crystallizes a lithographically defined region the film to obtain a region of laterally grown crystalline grains having at least one long grain boundary that is perpendicular to the lateral growth length; identifying the location of at least one long grain boundary; and manufacturing an electronic device in the semiconductor film at a location that is defined relative to the location of the long grain boundary.Type: ApplicationFiled: March 2, 2009Publication date: July 21, 2011Applicant: The Trustees of Columbia University in the City of New YorkInventor: James S. Im
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Publication number: 20110175141Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.Type: ApplicationFiled: December 9, 2010Publication date: July 21, 2011Inventors: Hajin LIM, Myungsun Kim, Hoi Sung Chung, Jinho Do, Weonhong Kim, Moonkyun Song, Dae-Kwon Joo
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Patent number: 7977712Abstract: A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.Type: GrantFiled: March 31, 2008Date of Patent: July 12, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Hong Lin, Katherine L. Saenger, Kai Xiu, Haizhou Yin
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Publication number: 20110163355Abstract: A method for manufacturing a field effect transistor, includes: forming a mask of an insulating film on a semiconductor layer containing Si formed on a semiconductor substrate; forming the semiconductor layer into a mesa structure by performing etching with the use of the mask, the mesa structure extending in a direction parallel to an upper face of the semiconductor substrate; narrowing a distance between two sidewalls of the mesa structure and flattening the sidewalls by performing a heat treatment in a hydrogen atmosphere, the two sidewalls extending in the direction and facing each other; forming a gate insulating film covering the mesa structure having the sidewalls flattened; forming a gate electrode covering the gate insulating film; and forming source and drain regions at portions of the mesa structure, the portions being located on two sides of the gate electrode.Type: ApplicationFiled: March 11, 2011Publication date: July 7, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Eiji Toyoda
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Publication number: 20110147805Abstract: A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Inventors: Toshifumi Irisawa, Shinichi Takagi, Naoharu Sugiyama
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Patent number: 7956360Abstract: A method of growing highly planar, fully transparent and specular m-plane gallium nitride (GaN) films. The method provides for a significant reduction in structural defect densities via a lateral overgrowth technique. High quality, uniform, thick m-plane GaN films are produced for use as substrates for polarization-free device growth.Type: GrantFiled: April 6, 2007Date of Patent: June 7, 2011Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Benjamin A. Haskell, Melvin B. McLaurin, Steven P. DenBaars, James Stephen Speck, Shuji Nakamura
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Publication number: 20110127639Abstract: The present disclosure relates to a semiconductor nanostructure. The semiconductor nanostructure includes a substrate and at least one ridge. The substrate includes a first crystal plane and a second crystal plane perpendicular to the first crystal plane. The at least one ridge extends from the first crystal plane along a crystallographic orientation of the second crystal plane. A width of cross section at a position of half the height of the at least one ridge is less than 17 nm. The semiconductor nanostructure is a patterned structure which can lead to generate a quantum confinement effect, such that the impurity scattering phenomenon is reduced.Type: ApplicationFiled: July 23, 2010Publication date: June 2, 2011Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: JIAN WU, ZHENG LIU, WEN-HUI DUAN, BING-LIN GU
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Publication number: 20110121434Abstract: A composition comprises a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate and at least one planar semiconductor nanowire epitaxially disposed on the substrate, where the nanowire is aligned along a crystallographic direction of the substrate parallel to the crystallographic plane. To fabricate a planar semiconductor nanowire, at least one nanoparticle is provided on a semiconductor substrate having a crystallographic plane oriented parallel to a surface of the substrate. The semiconductor substrate is heated within a first temperature window in a processing unit. Semi-conductor precursors are added to the processing unit, and a planar semiconductor nanowire is grown from the nanoparticle on the substrate within a second temperature window. The planar semiconductor nanowire grows in a crystallographic direction of the substrate parallel to the crystallographic plane.Type: ApplicationFiled: April 24, 2009Publication date: May 26, 2011Inventors: Xiuling Li, Seth A. Fortuna
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Publication number: 20110101422Abstract: A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.Type: ApplicationFiled: January 6, 2011Publication date: May 5, 2011Applicant: PANASONIC CORPORATIONInventor: Kaori AKAMATSU
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Publication number: 20110089473Abstract: A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.Type: ApplicationFiled: October 16, 2009Publication date: April 21, 2011Applicant: National Semiconductor CorporationInventor: Alexander H. Owens
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Patent number: 7928518Abstract: In a P-channel power MIS field effect transistor formed on a silicon surface having substantially a (110) plane, a gate insulation film is used which provides a gate-to-source breakdown voltage of 10 V or more, and planarizes the silicon surface, or contains Kr, Ar, or Xe.Type: GrantFiled: September 28, 2009Date of Patent: April 19, 2011Assignees: Yazaki CorporationInventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii, Takanori Watanabe
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Publication number: 20110073871Abstract: A gallium nitride substrate comprising a primary surface, the primary surface being tilted at an angle in a range of 20 to 160 degrees with respect to a C-plane of the substrate, and the substrate having a fracture toughness of more than or equal to 1.36 MN/m3/2.Type: ApplicationFiled: May 27, 2010Publication date: March 31, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Akihiro HACHIGO
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Patent number: 7915671Abstract: A semiconductor device includes a silicon substrate having a (110)-oriented surface, a PN column layer disposed on the (110)-oriented surface, a channel-forming layer disposed on the PN column layer, a plurality of source regions disposed at a surface portion of the channel-forming layer, and gate electrodes penetrate through the channel-forming layer. The PN column layer includes first columns having a first conductivity type and second columns having a second conductivity type which are alternately arranged in such a manner that the first columns contact the second columns on (111)-oriented surfaces, respectively. The gate electrodes are adjacent to the source regions, respectively, and each of the gate electrodes has side surfaces that cross the contact surfaces of the first columns and the second columns in a plane of the silicon substrate.Type: GrantFiled: May 13, 2008Date of Patent: March 29, 2011Assignee: DENSO CORPORATIONInventors: Takumi Shibata, Shouichi Yamauchi
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Publication number: 20110062446Abstract: Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45°-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.Type: ApplicationFiled: January 28, 2008Publication date: March 17, 2011Inventor: Amit Goyal
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Patent number: 7906415Abstract: An electronic device including: (a) a semiconductor layer including crystalline zinc oxide; and (b) an electrode including a suitable amount of zinc, indium, or a mixture thereof.Type: GrantFiled: July 28, 2006Date of Patent: March 15, 2011Assignee: Xerox CorporationInventors: Yuning Li, Beng S. Ong
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Publication number: 20110049681Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.Type: ApplicationFiled: August 31, 2009Publication date: March 3, 2011Inventor: Martin Henning Albrecht Vielemeyer
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Publication number: 20110037103Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.Type: ApplicationFiled: August 6, 2010Publication date: February 17, 2011Inventors: Tadashi YAMAGUCHI, Keiichiro KASHIHARA, Toshiaki TSUTSUMI, Tomonori OKUDAIRA, Kotaro KIHARA
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Patent number: 7888780Abstract: A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.Type: GrantFiled: January 15, 2010Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
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Publication number: 20110031592Abstract: Disclosed is a wafer having a good haze level in spite of the fact that the inclination angle of {110} plane in the wafer is small. Also disclosed is a method for producing a silicon epitaxial wafer, which comprises the steps of: growing an epitaxial layer on a silicon single crystal substrate having a main surface of {110} plane of which an off-angle is less than 1 degree; and polishing the surface of the epitaxial layer until the surface of the epitaxial layer has a haze level of 0.18 ppm or less (as measured by SP2 at a DWO mode).Type: ApplicationFiled: April 17, 2009Publication date: February 10, 2011Applicant: SUMCO CORPORATIONInventors: Masayuki Ishibashi, Shinji Nakahara, Tetsuro Iwashita
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Publication number: 20110001170Abstract: A semiconductor device according to the embodiment includes an element region provided with a transistor, a plurality of mixed crystal layers, a drain electrode and a source electrode, an element isolation layer and a dummy pattern. The mixed crystal layers are the layers made of a first atom composing the semiconductor substrate and a second atom having a lattice constant different from the lattice constant of the first atom and formed on both ends of a region, which becomes a channel of the transistor. The dummy pattern is a layer made of the same material as the mixed crystal layers and formed to extend on the surface of the semiconductor substrate and outside of the element region such that a major direction thereof is different from a <110> direction of the semiconductor.Type: ApplicationFiled: June 24, 2010Publication date: January 6, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takayuki Ito, Kunihiro Miyazaki, Kiyotaka Miyano
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Patent number: 7863712Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane <110> direction of the (011) DSB layer is aligned with an in-plane <110> direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane <100> directions of the (001) base substrate, followed by recrystallization using the base substrate as a template.Type: GrantFiled: October 30, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Haizhou Yin, John A. Ott, Katherine L. Saenger, Chun-Yung Sung
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Patent number: 7863713Abstract: For equalizing the rising and falling operating speeds in a CMOS circuit, it is necessary to make the areas of a p-type MOS transistor and an n-type MOS transistor different from each other due to a difference in carrier mobility therebetween. This area unbalance prevents an improvement in integration degree of semiconductor devices. The NMOS transistor and the PMOS transistor each have a three-dimensional structure with a channel region on both the (100) plane and the (110) plane so that the areas of the channel regions and gate insulating films of both transistors are equal to each other. Accordingly, it is possible to make the areas of the gate insulating films and so on equal to each other and also to make the gate capacitances equal to each other. Further, the integration degree on a substrate can be improved twice as much as that in the conventional technique.Type: GrantFiled: December 20, 2006Date of Patent: January 4, 2011Assignees: Tohoku University, Foundation for Advancement of International ScienceInventors: Tadahiro Ohmi, Akinobu Teramoto, Kazufumi Watanabe
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Publication number: 20100327329Abstract: According to one embodiment, a semiconductor device includes a transistor, an element isolation insulating film, and a metal silicide layer. The transistor contains a gate electrode and an epitaxial crystal layer. The epitaxial crystal layer is formed on at least one side of the gate electrode in the semiconductor substrate and includes a facet having a different plane direction from a principal plane of the semiconductor substrate. The element isolation insulating film contains a lower layer and an upper layer. A horizontal distance between the upper layer and the gate electrode is smaller than a horizontal distance between the lower layer and the gate electrode. A part of the upper layer contacts with the facet. The metal silicide layer is formed on an upper surface of the epitaxial crystal layer and on a region of the facet above a contact portion of the facet with the upper layer.Type: ApplicationFiled: June 16, 2010Publication date: December 30, 2010Inventor: Hiroshi ITOKAWA
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Publication number: 20100320505Abstract: A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face.Type: ApplicationFiled: June 3, 2010Publication date: December 23, 2010Applicant: FUJITSU LIMITEDInventors: Naoya OKAMOTO, Atsushi Yamada
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Publication number: 20100314722Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.Type: ApplicationFiled: February 19, 2009Publication date: December 16, 2010Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
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Publication number: 20100314670Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.Type: ApplicationFiled: May 27, 2010Publication date: December 16, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Marie Denison, Seetharaman Sridhar, Sameer Pendharkar, Umamaheswari Aghoram
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Patent number: 7842982Abstract: A semiconductor device includes a semiconductor substrate having, on a surface thereof, a (110) surface of Si1-xGex (0.25?x?0.90), and n-channel and p-channel MISFETs formed on the (110) surface, each MISFET having a source region, a channel region and a drain region. Each MISFET has a linear active region which is longer in a [?110] direction than in a [001] direction and which has a facet of a (311) or (111) surface, the source region, the channel region and the drain region are formed in this order or in reverse order in the [?110] direction of the linear active region, the channel region of the n-channel MISFET is formed of Si and having uniaxial tensile strain in the [?110] direction, and the channel region of the p-channel MISFET being formed of Si1-yGey (x<y?1) and having uniaxial compressive strain in the [?110] direction.Type: GrantFiled: January 28, 2009Date of Patent: November 30, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiko Moriyama, Naoharu Sugiyama
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Publication number: 20100289063Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.Type: ApplicationFiled: September 17, 2008Publication date: November 18, 2010Applicant: Centre Natinal De La Recherche Scientifique (C.N.R.S)Inventors: Guillaume Saint-Girons, Ludovic Largeau, Gilles Patriarche, Philippe Regreny, Guy Hollinger
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Patent number: 7834425Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.Type: GrantFiled: May 5, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Meikei Ieong, Xinlin Wang, Min Yang
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Publication number: 20100283089Abstract: Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a <110> crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the <110> crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.Type: ApplicationFiled: July 20, 2010Publication date: November 11, 2010Applicants: International Business Machines Corporation, GLOBAL FOUNDRIES, INC.Inventors: Yun-Yu Wang, Christopher D. Sheraw, Anthony G. Domenicucci, Linda Black, Judson R. Holt, David M. Fried
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Patent number: 7829898Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.Type: GrantFiled: February 14, 2006Date of Patent: November 9, 2010Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ootsuka, Tetsuya Takami, Tadaharu Minato
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Patent number: 7821098Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor structure further includes a blocking layer on the {100} side wall surfaces and the {110} side wall surfaces. The method further comprises the steps of removing portions of the blocking layer on the {110} side wall surfaces without removing portions of the blocking layer on the {100} side wall surfaces such that the {110} side wall surfaces are exposed to a surrounding ambient.Type: GrantFiled: April 15, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni
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Publication number: 20100264517Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard to pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.Type: ApplicationFiled: June 25, 2010Publication date: October 21, 2010Applicant: PANASONIC CORPORATIONInventors: Masayuki KURODA, Tetsuzo UEDA