Abstract: An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.

Abstract: In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.

Abstract: An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature.

Abstract: A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors.

Abstract: A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well.

Abstract: A filler for filling a gap includes a compound represented by the following Chemical Formula 1. SiaNbOcHd.??[Chemical Formula 1] In Chemical Formula 1, a, b, c, and d represent relative amounts of Si, N, 0, and H, respectively, in the compound, 1.96<a<2.68, 1.78<b<3.21, 0?c<0.19, and 4<d<10.

Abstract: A semiconductor device includes a semiconductor body including a first surface, an inner region and an edge region, a first doped device region of a first doping type in the inner region and the edge region, a second device region forming a device junction in the inner region with the first device region, and a plurality of at least two dielectric regions extending from the first surface into the semiconductor body. Two dielectric regions that are adjacent in a lateral direction of the semiconductor body are separated by a semiconductor mesa region. The semiconductor device further includes a resistive layer connected to the second device region and connected to at least one semiconductor mesa region.

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract: A device (10) to detect and measure static electric charge (q) on an object (100) being positioned in a distance (r.) from an input electrode (11) of the device (10) comprises at least one MOS field transistor (20). The input electrode (11) is connected with the gate electrode (21) of the MOS-FET (20) to detect said electrical charge. The MOS-FET (20) can comprise a gate oxide layer underneath the gate (21) and over the source (22) and drain (23) areas having a sufficient thickness to allow the MOS field transistor (20) to withstand several kilovolts (kV) of voltage and to avoid the loss of charges by tunnel effect due to the high potential of the gate electrode during ESD events.

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract: In one aspect, the present invention comprises an electrostatic discharge (ESD) protection circuit comprising a plurality of input circuits in which each input circuit comprises a first PMOS and a first NMOS transistor connected in series between a power supply and ground and first and second inverters connected to the gates of the first PMOS and NMOS transistors. Each inverter connected to the gate of the first NMOS transistor comprises a second NMOS transistor connected between that gate and ground and the ratio of the width of the gate of the second NMOS transistor to the width of the gate of the first NMOS transistor of each of the input circuits is substantially the same. In another aspect of the invention, a multi-fingered gate transistor is formed in a first well of one conductivity type that is surrounded by a second well of the same conductivity type from which it is separated by a shallow trench isolation and a portion of the substrate.

Abstract: A method for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET includes fabricate numerous trench MOSFETs on a wafer; add a Si3N4 isolation layer, capable of preventing the LTO patterning process from damaging the gate oxide, atop the wafer; add numerous ESD protection modules atop the Si3N4 isolation layer.

Abstract: A filler for filling a gap includes a hydrogenated polysiloxazane having an oxygen content of about 0.2 to about 3 wt %. A chemical structure of the hydrogenated polysiloxazane includes first, second, and third moieties represented by the following respective Chemical Formulas 1-3: The third moiety is on a terminal end of the hydrogenated polysiloxazane, and an amount of the third moiety is about 15 to about 35% based on a total amount of Si—H bonds in the hydrogenated polysiloxazane.

Abstract: To provide a semiconductor device that exhibits a high breakdown voltage, excellent thermal properties, a high latch-up withstanding capability and low on-resistance. The semiconductor device according to the invention, which includes a buried insulator region 5 disposed between an n?-type drift layer 3 and a first n-type region 7 above n?-type drift layer 3, facilitates limiting the emitter hole current, preventing latch-up from occurring, raising neither on-resistance nor on-voltage. The semiconductor device according to the invention, which includes a p-type region 4 disposed between the buried insulator region 5 and n?-type drift layer 3, facilitates depleting n?-type drift layer 3 in the OFF-state of the device.

Abstract: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.

Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: Dielectric layers having an atomic layer deposited oxide containing titanium and zirconium and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Pulsing a titanium-containing precursor onto a substrate, and pulsing a zirconium-containing precursor to form an oxide containing Zr and Ti by atomic layer deposition provides a dielectric layer with a relatively high dielectric constant as compared with silicon oxide. A zirconium-containing precursor to form the oxide containing Zr and Ti can include zirconium tertiary-butoxide.

Abstract: A semiconductor power device supported on a semiconductor substrate includes an electrostatic discharge (ESD) protection circuit disposed on a first portion of patterned ESD polysilicon layer on top of the semiconductor substrate. The semiconductor power device further includes a second portion of the patterned ESD polysilicon layer constituting a body implant ion block layer for blocking implanting body ions to enter into the semiconductor substrate below the body implant ion block layer. In an exemplary embodiment, the electrostatic discharge (ESD) polysilicon layer on top of the semiconductor substrate further covering a scribe line on an edge of the semiconductor device whereby a passivation layer is no longer required manufacturing the semiconductor device for reducing a mask required for patterning the passivation layer.

Abstract: The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002-0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: A device structure is disclosed for preventing gate oxide damage of a trench MOSFET during wafer processing while adding an ESD protection module atop the trench MOSFET. The ESD protection module has a low temperature oxide (LTO) bottom layer whose patterning process was found to cause the gate oxide damage before. The present invention structure includes a semiconductor substrate having an active area and a termination area; numerous trench MOSFET cells disposed in the active area; numerous electrostatic discharge (ESD) diodes disposed above the semiconductor substrate in the termination area; and an insulation layer comprising Oxide/Nitride/Oxide (ONO) sandwiched between the ESD diodes and the semiconductor substrate. In one embodiment, the active area does not contain the ONO insulation layer.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A field effect transistor includes a pair of ohmic electrodes and an n-type GaAs layer between the pair of ohmic electrodes and having recesses. Crank-shaped gate fingers are located within the recesses of the n-type GaAs layer between the pair of ohmic electrodes, and each crank-shaped gate finger includes perpendicular-extending portions and parallel-extending portions relative to the [0, 1, 1] crystal orientation of the n-type GaAs layer. The portion of the n-type GaAs layer between the gate fingers continuously extends from input ends of the gate electrodes to terminal ends of the gate electrode. A non-active region is located around each perpendicular-extending portion of the gate fingers.

Abstract: The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor device having a pre-metal dielectric liner. In embodiments, method for forming a semiconductor device may include forming a pre-metal dielectric liner, which has a multi-layer structure including a plurality of interfacial surfaces, on an entire surface of a semiconductor substrate formed with a transistor, and forming a boron phospho silicate glass (BPSG) oxide layer on the pre-metal dielectric liner. Since the pre-metal dielectric liner is formed in a multi-layer structure having a plurality of interfacial surfaces, boron (B) of an upper BPSG oxide layer is not penetrated into the semiconductor substrate.

Abstract: A method and apparatus are provided for protecting a semiconductor device from damage. The method includes the steps of providing a active semiconductor device on a surface of the semiconductor substrate where the active device is surrounded by inactive semiconductor areas and providing a soft metallic guard ring only in the inactive semiconductor areas around the periphery of the active device wherein the metallic guard ring is connected to ground potential and not to the active device.

Abstract: A semiconductor device has a semiconductor (e.g., a silicon substrate), an electrically conductive region (e.g., a source region and a drain region) which is in contact with the semiconductor to form a Schottky junction, and an insulator. The insulator is in contact with the semiconductor and the electrically conductive region, and has a fixed-charge containing region which contains a fixed charge and extends across a boundary between the semiconductor and the electrically conductive region.

Abstract: An insulating film includes an oxide or an oxynitride of a constituent element having a positive valence. The oxide or the oxynitride contains an additive element having a larger valence than the constituent element in a range not less than 3×10?8 at % and less than 1.6×10?3 at %.

Abstract: To provide a dielectric thin with a high dielectric constant, a low leakage current, and stable physical properties and electrical properties and to provide a thin film capacitor or other thin film dielectric device with a high capacitance and high reliability and a method of production of the same, a dielectric thin film containing oxides such as barium strontium titanate expressed by the formula (BaxSr(1-x))aTiO3 (0.5<x?1.0, 0.96<a?1.00) and having a thickness of not more than 500 nm and a method of production of a thin film dielectric device including a step of annealing the dielectric thin film in an atmosphere of an oxidizing gas after forming a dielectric thin film on a conductive electrode.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

Abstract: A silicon oxynitride film is manufactured using SiH4, N2O and H2 by plasma CVD, and it is applied to the gate insulating film (1004 in FIG. 1A) of a TFT. The characteristics of the silicon oxynitride film are controlled chiefly by changing the flow rates of N2O and H2. A hydrogen concentration and a nitrogen concentration in the film can be increased by the increase of the flow rate of H2. Besides, the hydrogen concentration and the nitrogen concentration in the film can be decreased to heighten an oxygen concentration by the increase of the flow rate of N2O. The gate insulating film ensures the stability and reliability of the characteristics of the TFT, such as the threshold voltage (Vth) and sub-threshold constant (S value) thereof.

Abstract: By forming a tensile silicon dioxide layer on the basis of a sub-atmospheric deposition technique, the strain-inducing mechanism of a tensile contact etch stop layer for N-channel transistors may be significantly improved. Consequently, for otherwise identical stress conditions, the performance of a respective N-channel transistor may be significantly enhanced.

Abstract: A dielectric device comprises a dielectric layer and first to nth metal layers (where n is an integer of 2 or greater) in contact with the dielectric layer. At least one of the first to nth metal layers contains a base metal. Interfaces between the first to nth metal layers and the dielectric layer have respective arithmetic mean roughnesses of Ra1 to Ran (nm), while an average value Ram (nm) of the arithmetic mean roughnesses of Ra1 to Ran (nm) and a thickness T (nm) of the dielectric layer satisfy T/Ram?1.3.

Abstract: A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.

Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

Abstract: According to an aspect of the present invention, there is disclosed a semiconductor device comprising a semiconductor substrate, and a gate insulating film of a P-channel MOS transistor, formed on the semiconductor substrate. The gate insulating film has an oxide film (SiO2), and a diffusion preventive film (BN) containing boron and nitrogen atoms.

Abstract: A multilayer printed circuit board (PCB) includes a substrate; a ground layer having edges which define a gap portion, the ground layer being provided on a bottom face of the substrate; and at least two signal traces and provided on a top face of the substrate so as to straddle the gap portion and so as to be substantially parallel to each other. The multilayer PCB also includes at least one ground trace provided between the at least two signal traces and on the top face of the substrate so as to straddle the gap portion.