Characterized By Specified Shape Or Size Of Pn Junction Or By Specified Impurity Concentration Gradient Within The Device (epo) Patents (Class 257/E29.005)

  • Patent number: 9653651
    Abstract: A light emitting device that is inexpensive, is easy to manufacture, and has high light extraction efficiency is provided. The light emitting device includes an oriented polycrystalline substrate, a plurality of columnar light emitting parts, and a light confinement layer. The oriented polycrystalline substrate includes a plurality of oriented crystal grains. The plurality of columnar light emitting parts are discretely located on or above one main surface of the oriented polycrystalline substrate in areas in which there are no crystal defects, and are each a columnar part having a longitudinal direction matching a normal direction of the oriented polycrystalline substrate. The light confinement layer is made of a material having a lower refractive index than a material for the plurality of columnar light emitting parts, and is located on or above the oriented polycrystalline substrate so as to surround the plurality of columnar light emitting parts.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 16, 2017
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yoshitaka Kuraoka, Shohei Oue, Masahiko Namerikawa, Morimichi Watanabe
  • Patent number: 9478611
    Abstract: An example semiconductor structure comprises a first surface and at least one nanowire, the at least one nanowire being perpendicular to the first surface, wherein the first surface is defect-poor and is made of a doped III-V semiconductor material, wherein the at least one nanowire is defect-poor and made of an undoped III-V semiconductor material having a lattice mismatch with the material of the first surface of from about 0% to 1%.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: October 25, 2016
    Assignee: IMEC VZW
    Inventors: Boon Teik Chan, Clement Merckling
  • Patent number: 9018617
    Abstract: A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0<x<1, 0<y<2. Values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi. The magnetically doped TI quantum well film is in 3 QL to 5 QL.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: April 28, 2015
    Assignees: Tsinghua University, Institute of Physics, Chinese Academy of Sciences
    Inventors: Qi-Kun Xue, Ke He, Xu-Cun Ma, Xi Chen, Li-Li Wang, Cui-Zu Chang, Xiao Feng, Yao-Yi Li, Jin-Feng Jia
  • Patent number: 9018616
    Abstract: A rectifying antenna device is disclosed. The device comprises a pair of electrode structures, and at least one nanostructure diode contacting at least a first electrode structure of the pair and being at least in proximity to a second electrode structure of the pair. At least one electrode structure of the pair receives AC radiation, and the nanostructure diode(s) at least partially rectifies a current generated by the AC radiation.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: April 28, 2015
    Assignee: Ramot at Tel-Aviv University Ltd.
    Inventors: Yael Hanein, Amir Boag, Jacob Scheuer, Inbal Friedler
  • Patent number: 9006707
    Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Jack T. Kavalieros, Suman Datta, Marko Radosavljevic
  • Patent number: 8987070
    Abstract: A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth
  • Patent number: 8946068
    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Devendra Sadana, Lidija Sekaric
  • Patent number: 8921850
    Abstract: A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: SangHee Yu
  • Patent number: 8918988
    Abstract: Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mohammed Fazil Fayaz, Jeffery Burton Maxson, Anthony Kendall Stamper, Daniel Scott Vanslette
  • Patent number: 8907405
    Abstract: Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Vega, Hongwen Yan
  • Patent number: 8907455
    Abstract: A voltage-controlled switch comprises a first electrode, a second electrode, a switching junction situated between the first electrode and the second electrode, a conducting channel extending from adjacent to the origin through the switching junction and having a channel end situated near the second electrode, and a layer of dopants situated adjacent to an interface between the switching junction and the second electrode, wherein the dopants are capable of being activated to form switching centers.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: December 9, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Julien Borghetti, Matthew D. Pickett
  • Patent number: 8901638
    Abstract: A trench-gate semiconductor device is disclosed, in which the player (10,6) which forms the body region (in a n-channel device) extends adjacent the trench (4) deeper into the device, to lie adjacent a lower trench electrode (3b, 3c). Since the p-layer extension (6) forms part of the channel, it must be very low doped, in order not to increase unduly the channel resistance in the on-state. The replacement of some of the out-diffusion resistance in the drift region by the (smaller) channel resistance results in a lower over-all Rdson. In the off-state, the p-layer forms, together with the underlying n-drift layer, a non-abrupt function, so that the depletion region in the off-state extends closer to the top surface (2) than for a conventional RSO trench-MOS, being split between the p- and n-layers, rather than all being in the n-drift region.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: December 2, 2014
    Assignee: NXP B.V.
    Inventors: Steven Thomas Peake, Phil Rutter
  • Patent number: 8901717
    Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: December 2, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Gerald Deboy
  • Patent number: 8895337
    Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Patent number: 8859399
    Abstract: A method of at least partially releasing an epitaxial layer of a material from a substrate. The method comprises the steps of: forming a patterned sacrificial layer on the substrate such that the substrate is partially exposed and partially covered by the sacrificial layer; growing the epitaxial layer on the patterned sacrificial layer by nano-epitaxial lateral overgrowth such that the epitaxial layer is formed above an intermediate layer comprising the patterned sacrificial layer and said material; and selectively etching the patterned sacrificial layer such that the epitaxial layer is at least partially released from the substrate.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: October 14, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Keyan Zang, Jinghua Teng, Soo Jin Chua
  • Patent number: 8829640
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 8803278
    Abstract: A semiconductor device includes a semiconductor substrate, a surface electrode formed on the semiconductor substrate, an ineffective region formed to surround the surface electrode, and an ID-indicating portion made of a different material than the surface electrode and formed on the surface electrode to indicate an ID. The area of the ineffective region is smaller than the area of the surface electrode.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: August 12, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasuo Ata, Takahiro Okuno, Tetsujiro Tsunoda
  • Patent number: 8785911
    Abstract: Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhihong Chen, Aaron Daniel Franklin, Shu-Jen Han, James Bowler Hannon, Katherine L. Saenger, George Stojan Tulevski
  • Patent number: 8759870
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: June 24, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
  • Patent number: 8759153
    Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: June 24, 2014
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Guenther Ruhl, Horst Theuss, Irmgard Escher-Poeppel
  • Patent number: 8748860
    Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Su Jin Chae, Jin Hyock Kim, Young Seok Kwon
  • Publication number: 20140117503
    Abstract: Compositions suitable for temporarily bonding two surfaces, such as a wafer active side and a substrate, are disclosed. Methods of temporarily bonding two surfaces, such as the active side of a wafer and a substrate using the compositions disclosed herein are also provided.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Mark S. OLIVER, Michael K. GALLAGHER
  • Publication number: 20140091434
    Abstract: Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: John D. Hopkins
  • Patent number: 8685774
    Abstract: A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: April 1, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Patent number: 8680581
    Abstract: The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 25, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoyuki Nakada, Koji Okuno, Yasuhisa Ushida
  • Publication number: 20140070373
    Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Nien-Yu Tsai, Wei Ming Chen
  • Publication number: 20140070358
    Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Puneet Khanna, Srikanth Samavedam, Vara G. Vakada, Michael P. Ganz, Sri Charan Vemula, Laegu Kang, Bharat V. Krishnan
  • Publication number: 20140070357
    Abstract: A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Balasubramanian S. Haran, Shom Ponoth
  • Patent number: 8669544
    Abstract: Amongst the candidates for very high efficiency solid state light sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group IIIA-nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. According to other embodiments of the invention self-organizing dot-within-a-dot nanowire and dot-within-a-dot-within-a-well nanowire structures are presented.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: March 11, 2014
    Assignee: The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Zetian Mi, Kai Cui, Hieu Pham Trung Nguyen
  • Publication number: 20140061793
    Abstract: A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chengwen Pei, Kangguo Cheng, Joseph Ervin, Juntao Li, Ravi M. Todi, Geng Wang
  • Publication number: 20140054551
    Abstract: A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric.
    Type: Application
    Filed: August 29, 2012
    Publication date: February 27, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Damon Farmer
  • Publication number: 20140048764
    Abstract: A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions. The amorphous alumina portions are removed and the remaining dense alumina portions which have an ordered lattice arrangement are employed as an etch mask. After removing the amorphous alumina portions, each dense alumina portion has a width which is also less than 10 nm.
    Type: Application
    Filed: September 8, 2012
    Publication date: February 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christos D. Dimitrakopoulos, Aaron D. Franklin, Joshua T. Smith
  • Publication number: 20140042593
    Abstract: A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Reinhard Ploss, Hans-Joachim Schulze
  • Patent number: 8648328
    Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Publication number: 20140021590
    Abstract: A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Johannes Laven, Dieter Fuchs, Werner Schustereder, Roman Knoefler
  • Patent number: 8633561
    Abstract: A superjunction device that includes a termination region having a transition region adjacent the active region thereof, the transition region including a plurality of spaced columns.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: January 21, 2014
    Assignee: Siliconix Technology C. V.
    Inventors: Ali Husain, Srinkant Sridevan
  • Patent number: 8633570
    Abstract: A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: January 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Naoki Okuno
  • Publication number: 20140015107
    Abstract: Closed loop control may be used to improve uniformity of within wafer uniformity using chemical mechanical planarization. For example, closed loop control may be used to determine a control profile for a chemical mechanical planarization process to more uniformly and consistently achieve the desired extent of variation of within wafer uniformity of a semiconductor wafer.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ching-Kun Chen, Chun-Fu Chen, Chin-Ta Su
  • Patent number: 8618608
    Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: December 31, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Ta-Cheng Lin, Te-Chang Wu
  • Patent number: 8618606
    Abstract: Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: December 31, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Tomomitsu Risaki, Shoji Nakanishi, Koichi Shimazaki
  • Publication number: 20130334651
    Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicants: International Business Machines Corporation, STMicroelectronic, Inc., Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Bruce B. Doris, Shom Ponoth, Prasanna Khare, Qing Liu, Nicolas Loubet, Maud Vinet
  • Patent number: 8610125
    Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Nano-Electronic and Photonic Devices and Circuits, LLC
    Inventor: Alexander Kastalsky
  • Patent number: 8610105
    Abstract: Provided is a semiconductor electroluminescent device with an InGaAlAs-based well layer having tensile strain, or a semiconductor electroluminescent device with an InGaAsP-based well layer having tensile strain and with an InGaAlAs-based barrier layer which is high-performance and highly reliable in a wide temperature range. In a multiple-quantum well layer of the semiconductor electroluminescent device, a magnitude of interface strain at an interface between the well layer and the barrier layer is smaller than a magnitude of critical interface strain determined by a layer thickness value which is larger one of a thickness of the well layer and a thickness of the barrier layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 17, 2013
    Assignee: Oclaro Japan, Inc.
    Inventors: Toshihiko Fukamachi, Takashi Shiota, Takeshi Kitatani, Nozomu Yasuhara, Atsushi Nakamura, Mitsuhiro Sawada
  • Patent number: 8610104
    Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on semiconductor wafers, the CNT-based devices can be combined with the conventional semiconductor circuit elements, thus producing hybrid devices and circuits.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Nano-Electronic and Photonic Devices and Circuits, LLC
    Inventor: Alexander Kastalsky
  • Publication number: 20130312819
    Abstract: A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell.
    Type: Application
    Filed: June 26, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Keith E. Fogel, Bahman Hekmatshoartabari, Paul A. Lauro, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20130292805
    Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 7, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiuyu CAI, Ruilong XIE, William J. TAYLOR, JR.
  • Patent number: 8569836
    Abstract: A semiconductor device includes an output port that has a first lateral double diffused metal oxide semiconductor (LDMOS) device and an electrostatic discharge protection device that has a second LDMOS device and a bipolar transistor and that protects the output port from electrostatic discharge. A breakdown voltage of the second LDMOS device is equal to or lower than a breakdown voltage of the first LDMOS device.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Mueng-Ryul Lee
  • Patent number: 8569098
    Abstract: A method for manufacturing a photoelectric conversion device including a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, and a second-conductivity-type semiconductor region that are stacked over an electrode is provided for a new anti-reflection structure. An interface between the electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. The first-conductivity-type crystalline semiconductor region and the intrinsic crystalline semiconductor region are formed by a low pressure chemical vapor deposition method at a temperature higher than 550° C. and lower than 650° C.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20130270511
    Abstract: Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
    Type: Application
    Filed: April 12, 2012
    Publication date: October 17, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Yanqing Wu, Wenjuan Zhu
  • Publication number: 20130263918
    Abstract: Photovoltaic nanocomposite and solar cell device including the photovoltaic nanocomposite, where the photovoltaic nanocomposite includes a film of solution processed semiconductor materials having an n-type material selected from n-type quantum dots and n-type nanocrystals, and a p-type material selected from p-type quantum dots and p-type nanocrystals, and where the n-type material has a conduction band level at least equal, compared to vacuum level, to that of the p-type material, the p-type material has a valence band at the most equal, compared to vacuum level, to that of the n-type material. at least a portion of the n-type material and at least a portion of the p-type material are present in a bulk nano-heterojunction binary nanocomposite layer having a blend of the n-type material and the p-type material.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Applicant: FUNDACIÓ INSTITUT DE CIÈNCIES FOTÒNIQUES
    Inventors: GERASIMOS KONSTANTATOS, ARUP KUMAR RATH, MARIA BERNECHEA NAVARRO, LUIS MARTINEZ MONTBLANCH