Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.

Abstract: An optoelectronic semiconductor chip includes a semiconductor layer sequence having at least one doped functional layer having at least one dopant and at least one codopant, wherein the semiconductor layer sequence includes a semiconductor material having a lattice structure, one selected from the dopant and the codopant is an electron acceptor and the other an electron donor, the codopant is bonded to the semiconductor material and/or arranged at interstitial sites, and the codopant at least partly forms no bonding complexes with the dopant.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A device includes a well region over a substrate, and a heavily doped well region over the well region, wherein the well region and the heavily doped well region are of a same conductivity type. A gate dielectric is formed on a top surface of the heavily doped well region. A gate electrode is formed over the gate dielectric. A source region and a drain region are formed on opposite sides of the heavily doped well region. The source region and the drain region have bottom surfaces contacting the well region, and wherein the source region and the drain region are of opposite conductivity types.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein the edge termination area comprises a wide trench filled with a field-crowding reduction filler and a buried field plate buried under a top surface of the semiconductor substrate and laterally extended over a top portion of the field crowding field to move a peak electric field laterally away from the active cell area. In a specific embodiment, the field-crowding reduction filler comprises a silicon oxide filled in the wide trench.

Abstract: A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)A(IIXIIIYIVZ)(1-A), where I is at least one of As and Se, II is at least one of Ge, Si and Sn, III is at least one of Sb and Bi, and IV is at least one of Te and Se, and where 0.001?A?0.3, 0.001?X?0.3, 0.001?Y?0.8, 0.1?Z?0.8, and X+Y+Z=1.

Abstract: The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property. The present invention provides a semiconductor device comprising a resistance-variable element provided within multiple wiring layers on a semiconductor substrate, wherein the resistance-variable element comprises a laminated structure in which a first electrode, a first ion-conductive layer of valve-metal oxide film, a second ion-conductive layer containing oxygen and a second electrode are laminated in this order, and the wiring of the multiple wiring layers also serves as the first electrode.

Abstract: A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate.

Abstract: A composition comprising a material at least partially enclosed by a tubular, spherical or planar nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid.

Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.

Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.

Abstract: A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.

Abstract: A guard ring structure for use in a semiconductor device. The guard ring structure includes a semiconductor layer stack having a first layer and a second layer on top of the first layer, gates structures formed in the first layer; and guard rings formed in the first layer. The second layer has a dopant concentration that is higher than the dopant concentration of the first layer. The gates and the guard rings are formed simultaneously using a single mask.

Abstract: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow.

Abstract: A description is given of a normally on semiconductor component having a drift zone, a drift control zone and a drift control zone dielectric arranged between the drift zone and the drift control zone.

Abstract: Triphenylene containing benzo-fused thiophene compounds are provided. Additionally, triphenylene containing benzo-fused furan compounds are provided. The compounds may be useful in organic light emitting devices, particularly as hosts in the emissive layer of such devices, or as materials for enhancement layers in such devices, or both.

Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.

Abstract: A cell of a semiconductor device comprises a substrate of n-type with a trench formed in a portion of a first main surface of the substrate and filled with insulator. Two device-feature regions are formed beneath the first main surface of the substrate, the first one at one side and the second one at the other side of the trench. A region of a p-type and/or a region of metal is formed in the first device feature region and is connected to a first electrode. A p-n junction is formed in the second device feature region and the p-region of the p-n junction is connected to a second electrode. A U-shaped region is formed between the two device regions. An IGBT without tail during turning-off can be fabricated with a simple process at a low cost.

Abstract: This invention discloses semiconductor device that includes a top region and a bottom region with an intermediate region disposed between said top region and said bottom region with a controllable current path traversing through the intermediate region. The semiconductor device further includes a trench with padded with insulation layer on sidewalls extended from the top region through the intermediate region toward the bottom region wherein the trench includes randomly and substantially uniformly distributed nano-nodules as charge-islands in contact with a drain region below the trench for electrically coupling with the intermediate region for continuously and uniformly distributing a voltage drop through the current path.

Abstract: An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth.

Abstract: A semiconductor memory device is disclosed in which a layer containing an organic compound is interposed between a pair of electrodes and, further, a first layer including a first metal oxide and a second layer including a second metal oxide are interposed between the pair of electrodes. One of the two layers including the metal oxide acts as a p-type semiconductor layer and the other acts as an n-type semiconductor layer. The first layer including the first metal oxide and the second layer including the second metal oxide form a p-n junction, which provides rectification characteristic to the semiconductor memory device.

Abstract: A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb2Se3, and a metal-chalcogenide layer and methods of forming such a memory device.

Abstract: An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.

Abstract: A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

Abstract: Ambipolar conduction can be reduced in carbon nanotube transistors by forming a gate electrode of a metal. Metal sidewall spacers having different workfunctions than the gate electrode may be formed to bracket the metal gate electrode.

Abstract: A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with interface resistance-reduced source/drain electrodes is disclosed. This device includes a p-type MISFET formed on a semiconductor substrate. The p-MISFET has a channel region in the substrate, a gate insulating film on the channel region, a gate electrode on the gate insulating film, and a pair of laterally spaced-apart source and drain electrodes on both sides of the channel region. These source/drain electrodes are each formed of a nickel (Ni)-containing silicide layer. The p-MISFET further includes an interface layer which is formed on the substrate side of an interface between the substrate and each source/drain electrode. This interface layer contains magnesium (Mg), calcium (Ca) or barium (Ba) therein. A fabrication method of the semiconductor device is also disclosed.

Abstract: High-resistance elements are connected as parts of a control resistor between a switching element and a protecting element immediately near the switching element and between adjacent protecting elements. Paths for high-frequency signals are cut off, and high-frequency signals can be prevented from leaking although there are parasitic capacitances due to the protecting elements being connected. Accordingly, electrostatic breakdown voltage can be improved, and isolation can be prevented from deteriorating.

Abstract: The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.

Abstract: A semiconductor device that includes a phase change material for protecting the device from failure caused by overheating. The semiconductor device is adapted to detect a rapid increase in current due to heat and also adapted to break a circuit in the detected rapid increase in current by depositing a phase change material inside or outside a cell actually operated in the semiconductor device.

Abstract: An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material.

Abstract: A method of making a thin film transistor comprising a thin film semiconductor element comprised of a transparent zinc-oxide-based semiconductor material, wherein spaced apart first and second contacts in contact with said material are position on either side of a channel in the thin film semiconductor element such that the elongated sides of the channel are aligned with an underlying gate structure. The method can be accomplished while maintaining the substrate temperature at no more than 300° C. during fabrication.

Abstract: A light-emitting LED device has one or more light-emitting LED elements, including first and second spaced-apart electrodes with one or more light-emitting layers formed there-between, wherein at least one of the electrodes is a transparent electrode. Also included are a first transparent encapsulating layer having a first optical index formed over the transparent electrode opposite the light-emitting layer; a light-scattering layer formed over the first transparent encapsulating layer opposite the transparent electrode; and a second transparent encapsulating layer, having a second optical index lower than the first optical index, formed over the light-scattering layer.

Abstract: A conjugated or partially conjugated polymer including a structural unit of Formula (I); where T is an aryl or heteroaryl group that may be substituted or unsubstituted, or a C1-C24 alkyl group; R1 is alkyl, alkoxy, aryl group, cyano, or F; and a and b are independently selected from 1, 2 or 3. In addition, a composition of Formula (IV); wherein X is a halogen or a boronate group.

Abstract: An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer.

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract: A piezoresistive sensing structure includes an assembly formed of a semiconductor material and including a cavity and a plurality of piezoresistive elements implanted into the assembly. The assembly includes a central mass coupled to a peripheral frame with a plurality of beams. Each beam is about 15 microns in width and includes one of the piezoresistive elements. The assembly may also include a first wafer having the cavity formed into a first side, and a second wafer with a plurality of beams formed in a first side. The second side of the second wafer is bonded to the first side of the first wafer.

Abstract: A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin film spacer defines a sub-lithographic dimension and is electrically coupled between a second electrode and the first thin film spacer. In this regard, the phase change memory cell is formed at a boundary where the first thin film spacer electrically contacts the second thin film spacer.

Abstract: A heteroacene compound includes a di-thieno-benzo-thieno-thiophene derivative, in which all six rings may be fused together, an organic thin film including the same, and an electronic device that includes the thin film as a carrier transport layer. The compound of example embodiments may have a compact planar structure to thus realize improved solvent solubility and processability. When the compound is applied to electronic devices, a deposition process or a room-temperature solution process may be applied, and as well, intermolecular packing and stacking may be efficiently realized, resulting in improved electrical properties, including increased charge mobility.

Abstract: Disclosed are a ferrocene-containing conductive polymer, an organic memory device using the conductive polymer and a method for fabricating the organic memory device. The conductive polymer may include a fluorenyl repeating unit, a thienyl repeating unit and a diarylferrocenyl repeating unit. The organic memory device may possess the advantages of rapid switching time, decreased operating voltage, decreased fabrication costs and increased reliability. Based on these advantages, the organic memory device may be used as a highly integrated, large-capacity memory device.

Abstract: An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.

Abstract: A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A semiconductor memory device is disclosed in which a layer containing an organic compound is interposed between a pair of electrodes and, further, a first layer including a first metal oxide and a second layer including a second metal oxide are interposed between the pair of electrodes. One of the two layers including the metal oxide acts as a p-type semiconductor layer and the other acts as an n-type semiconductor layer. The first layer including the first metal oxide and the second layer including the second metal oxide form a p-n junction, which provides rectification characteristic to the semiconductor memory device.

Abstract: The invention concerns a photoactive nanocomposite (3) comprising at least one donor-acceptor couple of semiconductor elements. One of the elements is made of doped nanowires (7) with sp3 structure, and the other of the elements is an organic compound (8). The elements are supported by a device substrate (1). The invention also concerns a production method. According to a first embodiment, after their growth, the nanowires (7) are retrieved, functionalised and solubilised in the organic component (8). The mixture is deposited by coating on a device substrate. According to a second embodiment, the nanowires (7) are formed on a growth substrate (5) which is also the device substrate. The organic component (8) is combined with the nanowires (7) so as to form an active layer (3). Such a photoactive nanocomposite (3) allows production of a photovoltaic cell.

Abstract: An electronic circuit is formed by closely spacing metallic gate and drain interconnects to a flexible portion of a source interconnect. A gate voltage results in electrostatic attraction and lateral mechanical movement of the flexible source interconnect portion and causes an electrical short between source and drain. VanderWaals attraction between contacting source and drain can be used to provide volatile switching (springy thicker source portion) and non-volatile switching (limp thinner source portion). In accordance with the invention, an easily fabricated, high speed, low power, radiation hard, temperature independent, integrated reconfigurable electronic circuit with embedded logic and non-volatile memory can be realized. The switch uses patterned interconnect material for its structure and can be incorporated to a 3D layered structure consisting of three dimensional interconnect in which different layers and portions of the circuits are linked through volatile and non-volatile switches.

Abstract: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Abstract: A method for forming an improved isolation junction in an LDMOS structure to reduce current leakage at high operating Voltages including forming doped regions in a buried layer prior to forming an overlying epitaxial region including doped isolation regions followed by a drive-in process to form a continuous isolation region by intermixing the doped regions formed in the buried layer with the overlying doped isolation regions.