With Inactive Supplementary Region (e.g., For Preventing Punch-through, Improving Capacity Effect Or Leakage Current) (epo) Patents (Class 257/E29.063)
  • Patent number: 10361288
    Abstract: Fin field-effect transistors and fabrication methods are provided. An exemplary fabrication method includes providing a providing a plurality of fins on a surface of a semiconductor substrate; forming a gate structure across the fins by covering portions of top and side surfaces of the fins, wherein portions of the fins under the gate structure are channel regions; forming lightly doped regions in the fins at both sides of the gate structure by performing a lightly doping ion implantation process; performing a counter doping ion implantation process on a portion of each lightly doped region away from the channel region to form a counter doped region in the lightly doped region; and performing a source/drain doping process on the fins at both sides of the gate structure to form doped source/drain regions.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 9673190
    Abstract: A device having an electrostatic discharge structure includes a bulk substrate having a first dopant conductivity, first wells formed adjacent to a surface of the bulk substrate, including a second dopant conductivity, and second wells formed adjacent to the surface of the bulk substrate within the first wells, including the first dopant conductivity. A supply bus is formed in one of the first wells outside the second well. A ground bus has a first portion formed in another first well outside the second well, and a second portion is formed inside the second well such that a charge input to the second wells is dissipated without accumulating in the bulk substrate.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Terence B. Hook, Ali Khakifirooz, Pranita Kerber, Balasubramanian Pranatharthiharan, Ghavam G. Shahidi
  • Patent number: 9431516
    Abstract: MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: August 30, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8823051
    Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 2, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Micheal Harley-Stead, Jim G. Holt
  • Patent number: 8716790
    Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 6, 2014
    Assignee: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Jian Tan
  • Patent number: 8592923
    Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Tsung-Yi Huang, Fu-Jier Fan
  • Patent number: 8399953
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Kenji Gomikawa, Yoshiko Kato, Norihisa Arai, Tomoaki Hatano
  • Patent number: 8318570
    Abstract: A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ying Zhang
  • Patent number: 8278719
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include one or more parasitic isolation devices and/or buried layer structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: October 2, 2012
    Assignee: Silicon Space Technology Corp.
    Inventor: Wesley H. Morris
  • Patent number: 8227871
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 24, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Choul Joo Ko
  • Patent number: 8188523
    Abstract: An insulated gate field effect transistor, a solid-state image pickup device using the same, and manufacturing methods thereof that suppress occurrence of a shutter step and suppress occurrence of punch-through and injection. An insulated gate field effect transistor having a gate electrode on a semiconductor substrate with a gate insulating film interposed between the semiconductor substrate and the gate electrode, and having a source region and a drain region formed in the semiconductor substrate on both sides of the gate electrode, the insulated gate field effect transistor including: a first diffusion layer of a P type formed in the semiconductor substrate at a position deeper than the source region and the drain region; and a second diffusion layer of the P type having a higher concentration than the first diffusion layer and formed in the semiconductor substrate at a position deeper than the first diffusion layer.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventor: Hiroyuki Yoshida
  • Patent number: 8169028
    Abstract: In a conventional semiconductor device, protection of a to-be-protected element from a surge voltage is difficult because the to-be-protected element is turned on before a protection element due to variations in manufacturing conditions. In a semiconductor device of the present invention, a protection element and a MOS transistor have part of their structures formed under common conditions. N type diffusion layers of the protection element and the MOS transistor are formed in the same process, while the N type diffusion layer of the protection element has a larger diffusion width than the N type diffusion layer of the MOS transistor. With this structure, when a surge voltage is applied to an output terminal, the protection element is turned on before the MOS transistor, and thereby the MOS transistor is protected from an avalanche current.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 1, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Takashi Ogura
  • Patent number: 8049295
    Abstract: A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: November 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Liang Chou, Chen-Bau Wu, Weng-Chu Chu, Tsung-Yi Huang, Fu-Jier Fan
  • Patent number: 7968400
    Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: June 28, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 7956419
    Abstract: A very low VCEON non punch through trench IGBT built-in non-epitaxial float zone silicon has a depletion stop layer structure added to its bottom surface.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: June 7, 2011
    Assignee: International Rectifier Corporation
    Inventors: Richard Francis, Chiu Ng
  • Patent number: 7944017
    Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: May 17, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Mitsuo Hatamoto, Yoshiaki Matsumiya
  • Patent number: 7902606
    Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: John B. Campi, Jr., Richard A. Phelps, Robert M. Rassel, Michael J. Zierak
  • Patent number: 7880240
    Abstract: A semiconductor device has a high voltage circuit section disposed on a semiconductor substrate having a first conductivity. The high voltage circuit section has a well region with a second conductivity, a first heavily doped impurity region with the first conductivity and disposed on the well region, a second heavily doped impurity region having a second conductivity and disposed on the semiconductor substrate, a trench isolation region disposed between the first and second heavily doped impurity regions, and an interconnect disposed over the trench isolation region. First and second electrodes are disposed above the trench isolation region, below the interconnect, and on opposite sides of a junction between the well region and the semiconductor substrate. The first electrode is disposed above the semiconductor substrate, and the second electrode is disposed above the well region.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 1, 2011
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 7851316
    Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventor: Hiroyuki Kamada
  • Patent number: 7829939
    Abstract: A metal oxide semiconductor field effect transistor structure and a method for fabricating the metal oxide semiconductor field effect transistor structure provide for a halo region that is physically separated from a gate dielectric. The structure and the method also provide for a halo region aperture formed horizontally and crystallographically specifically within a channel region pedestal within the metal oxide semiconductor field effect transistor structure. The halo region aperture is filled with a halo region formed using an epitaxial method, thus the halo region may be formed physically separated from the gate dielectric. As a result, performance of the metal oxide semiconductor field effect transistor is enhanced.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Qingqing Liang, Jing Wang
  • Patent number: 7816734
    Abstract: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuck-Chai Jung, June-Hee Lim
  • Patent number: 7718480
    Abstract: In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: May 18, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Marcel ter Book, Peter J. Hopper
  • Patent number: 7687354
    Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 30, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
  • Patent number: 7682888
    Abstract: A method of forming an integrated circuit includes selectively forming active channel regions for NMOS and PMOS transistors on a substrate parallel to a <100> crystal orientation thereof and selectively forming source/drain regions of the NMOS transistors with Carbon (C) impurities therein.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Lee, Tetsuji Ueno, Hwa-Sung Rhe
  • Patent number: 7683421
    Abstract: A NAND-type flash memory device including selection transistors is provided. The device includes first and second impurity regions formed in a semiconductor substrate, and first and second selection gate patterns disposed on the semiconductor substrate between the first and second impurity regions. The first and second selection gate patterns are disposed adjacent to the first and second impurity regions, respectively. A plurality of cell gate patterns are disposed between the first and second selection gate patterns. A first anti-punchthrough impurity region that surrounds the first impurity region is provided in the semiconductor substrate. The first anti-punchthrough impurity region overlaps with a first edge of the first selection gate pattern adjacent to the first impurity region. A second anti-punchthrough impurity region that surrounds the second impurity region is provided in the semiconductor substrate.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gyoung-Ho Buh, Sun-Ghil Lee, Jong-Ryeol Yoo, Deok-Hyung Lee, Guk-Hyon Yon
  • Patent number: 7671358
    Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Mitchell C. Taylor
  • Patent number: 7615826
    Abstract: An electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided. The semiconductor structure has multi-stage protection semiconductor circuit function and adjustable discharge capacity. The single-trigger or multi-trigger semiconductor structure may be fabricated by using the conventional semiconductor process, and can be applied to IC semiconductor design and to effectively protect the important semiconductor devices and to prevent the semiconductor devices from ESD damage. In particular, the present invention can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit. In the present invention, a plurality of N-wells or P-wells connected in parallel are used to adjust the discharge capacity of various wells in the P-substrate so as to improve the ESD protection capability and meet different power standards.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: November 10, 2009
    Assignee: System General Corp.
    Inventors: Chih-Feng Huang, Tuo-Hsin Chien, Jenn-Yu G. Lin, Ta-yung Yang
  • Patent number: 7608515
    Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: October 27, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yu Chen, Shui-Ming Cheng
  • Patent number: 7602017
    Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 13, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 7598146
    Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics, Inc.
    Inventor: Robert Louis Hodges
  • Publication number: 20090221119
    Abstract: In a semiconductor fabrication process, an epitaxial layer is formed overlying a substrate, wherein there is a lattice mismatch between the epitaxial layer and the substrate. A hard mask having an opening is formed overlying the epitaxial layer. A recess is formed through the epitaxial layer and into the substrate. The recess is substantially aligned to the opening in the hard mask. A channel region of a semiconductor device is formed in the recess.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Inventors: Paul A. Grudowski, Veeraraghavan Dhandapani, Stefan Zollner
  • Patent number: 7579658
    Abstract: ESD protection devices without current crowding effect at the finger's ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the NMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 25, 2009
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ming-Dou Ker, Geeng-Lih Lin, Hsin-Chyh Hsu
  • Publication number: 20090140288
    Abstract: A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.
    Type: Application
    Filed: February 9, 2009
    Publication date: June 4, 2009
    Inventors: Zachary K. Lee, Farid Nemati, Scott Robins
  • Patent number: 7534689
    Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: May 19, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rohit Pal, Igor Peidous, David Brown
  • Patent number: 7521342
    Abstract: A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Bau Wu, Fang-Cheng Lui, Shun-Liang Hsu
  • Patent number: 7432551
    Abstract: An object is to increase the amount of substrate noise absorbed in a guard ring, and to prevent a malfunction caused by the substrate noise in a semiconductor device including an SOI substrate provided with the guard ring. Then, there is provided a semiconductor device, including: an SOI substrate in which a support substrate 10, an insulating layer 11, and an SOI layer 12 are stacked one by one; an element section 4 provided in one region of the SOI substrate; and a guard ring region 8 provided around the element section 4 of the SOI substrate, wherein a first diffusion layer 15 provided in the SOI layer 12 of the element section 4, and a second diffusion layer 26 provided in the SOI layer 12 of the guard ring region 8 are electrically connected to each other.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: October 7, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Ryota Yamamoto, Yutaka Akiyama, Masayuki Furumiya
  • Patent number: 7400016
    Abstract: In a semiconductor device, source/drain layers have a low resistivity region and an extension region extending from the low resistivity region toward the channel region. The extension regions are lower in impurity concentration and shallower in depth than the low resistivity regions. The device also has a first impurity-doped layer formed in the channel region between the source/drain layers, a second impurity-doped layer formed under the first impurity-doped layer, and a third impurity-doped layer formed under the second impurity-doped layer. The first impurity-doped layer is equal or less in junction depth than the extension regions. The second impurity doped layer has impurity concentration and thickness to be fully depleted due to a built-in potential as created between the first and third impurity-doped layers.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Inaba
  • Patent number: 7279767
    Abstract: A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Bau Wu, Fang-Cheng Lui, Shun-Liang Hsu
  • Publication number: 20060170060
    Abstract: A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.
    Type: Application
    Filed: February 3, 2005
    Publication date: August 3, 2006
    Inventors: Chen-Bau Wu, Fang-Cheng Lui, Shun-Liang Hsu