Abstract: The present disclosure provides a thin film transistor, a manufacturing method of the thin film transistor, and a liquid crystal display. The thin film transistor includes a substrate; an active region arranged above the substrate; a channel region arranged in a center of the active region; source and drain regions arranged on two sides of the channel region; a gate dielectric layer arranged above the channel region; a reflective coating arranged above the gate dielectric layer; a gate metal arranged above the reflective coating; an interlayer dielectric layer covering the gate metal, the active region, and the substrate; and a source/drain metal layer passing through the interlayer dielectric layer and electrically connecting with a surface of the source and drain regions.

Abstract: A semiconductor device including an oxide semiconductor film that includes a transistor with excellent electrical characteristics is provided. It is a semiconductor device including a transistor. The transistor includes a gate electrode, a first insulating film, an oxide semiconductor film, a source electrode, a drain electrode, and a second insulating film. The source electrode and the drain electrode each include a first conductive film, a second conductive film over and in contact with the first conductive film, and a third conductive film over and in contact with the second conductive film. The second conductive film contains copper, the first conductive film and the third conductive film include a material that inhibits diffusion of copper, and an end portion of the second conductive film includes a region containing copper and silicon.

Abstract: The disclosure relates to a method for making an iron telluride including placing Fe, Bi, and Te in a reacting chamber as reacting materials. The reacting chamber is evacuated to be a vacuum with a pressure lower than 10 Pa. The reacting chamber is heated to a first temperature of 700 degrees Celsius to 900 degrees Celsius and keeping the first temperature for a period of 10 hours to 14 hours. Then the reacting chamber is cooled to a second temperature of 400 degrees Celsius to 700 degrees Celsius within 60 hours to 75 hours and keeping the second temperature for a period of 40 hours to 50 hours, to obtain a reaction product including a FeTe0.9 single crystal. The FeTe0.9 single crystal is separated from the reaction product.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor including an oxide semiconductor film, the oxide semiconductor film is subjected to dehydration or dehydrogenation performed by heat treatment. In addition, as a gate insulating film in contact with the oxide semiconductor film, an insulating film containing oxygen, preferably, a gate insulating film including a region containing oxygen with a higher proportion than the stoichiometric composition is used. Thus, oxygen is supplied from the gate insulating film to the oxide semiconductor film. Further, a metal oxide film is used as part of the gate insulating film, whereby reincorporation of an impurity such as hydrogen or water into the oxide semiconductor is suppressed.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: The present invention is a method for producing a capacitor. The method includes applying a dielectric substance (ex.—silicon nitride) to a first gold seed layer, the first gold seed layer being formed on a wafer. A second gold seed layer is formed upon the dielectric substance and first gold seed layer. Gold is electroplated into a photoresist to form a first set of 3-D capacitor elements on the second gold seed layer. A first copper layer is electroplated onto the second gold seed layer. Gold is electroplated into a photoresist to form a second set of 3-D capacitor elements, the second set of 3-D elements being formed at least partially within the first copper layer and being connected to the first set of 3-D elements. A second copper layer is electroplated onto the first copper layer. Then, both copper layers are removed to provide (ex.—form) the capacitor.

Abstract: Provided are an oxide semiconductor and an oxide thin film transistor including the oxide semiconductor. The oxide semiconductor may be formed of an indium (In)-zinc (Zn) oxide in which hafnium (Hf) is contained, wherein In, Zn, and Hf are contained in predetermined or given composition ratios.

Abstract: Embodiments of the disclosed technology provide an array substrate comprising a plurality of pixel units each of which comprises a gate scanning line, a source scanning line, a thin film transistor (TFT), a storage capacitor, and at least one photosensitive transistor, wherein a gate electrode of the photosensitive transistor and a gate electrode of the TFT are connected with the same gate scanning line, a drain electrode of the photosensitive transistor and a drain electrode of the TFT are connected with the storage capacitor, a source electrode of the TFT is connected with the source scanning line, and a source electrode of the photosensitive transistor is connected with its own gate electrode. In addition, the embodiments of the disclosed technology also provide a liquid crystal panel comprising the array substrate and a display device comprising the liquid crystal panel.

Abstract: A nitride semiconductor device includes: a first layer made of a first nitride semiconductor; a second layer provided on the first layer and made of a second nitride semiconductor having a larger band gap than the first nitride semiconductor; a first electrode electrically connected to the second layer; a second electrode provided on the second layer and juxtaposed to the first electrode in a first direction; and a floating electrode provided on the second layer, the floating electrode including: a portion sandwiched by the second electrode in a second direction orthogonal to the first direction; and a portion protruding from the second electrode toward the first electrode.

Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.

Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Abstract: A pixel array includes scan lines, data lines, and pixels. Each pixel arranged in the nth row includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. In the first sub-pixel, a first gate and a first drain of a first transistor are connected to the (n?1)th scan line and a first pixel electrode, respectively. In the second sub-pixel, a second gate of a second transistor is connected to the nth scan line, and a second drain is connected to a second pixel electrode and a first source of the first transistor. In the third sub-pixel, a third gate of a third transistor is connected to the (n+1)th scan line, a third drain is connected to a third pixel electrode and a second source of the second transistor, and a third source is connected to one of the data lines.

Abstract: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf and Cr atoms added thereto.

Abstract: Provided is a liquid crystal display (LCD) device and a fabrication method thereof. An array substrate for the LCD includes a gate line formed on a substrate, and a gate electrode extending from the gate line; a data line intersected with the gate line, wherein the data line is configured with a gate insulating layer, a semiconductor layer and a data metal layer; a pixel electrode formed of a first transparent metal layer at a pixel which is defined by an intersection of the gate line and the data line; a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance to expose a channel; and a second transparent metal layer pattern formed on the data line, the source electrode and the drain electrode, wherein the second transparent metal layer connects the drain electrode and the pixel electrode to each other.

Abstract: A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved.

Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver circuit are provided over the same substrate, manufacturing cost can be reduced.

Abstract: A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO2 mask into stripes oriented in the gallium nitride <1 100> or <11 20> direction; (3) growing epitaxial lateral overgrowth of (ELO) gallium nitride layers by controlling the facet planes via choosing the growth temperature and the reactor; (4) depositing zinc oxide films on facets ELO gallium nitride templates by chemical vapor deposition (CVD). Zinc oxide crystal of high quality with a reduced number of crystal defects can be grown on a gallium nitride template. This method can be used to fabricate zinc oxide films with low dislocation density lower than 104/cm?2, which will find important applications in future electronic and optoelectronic devices.

Abstract: Disclosed is a resistive memory device. In the resistive memory device, at least one variable resistance region and at least one switching device may be horizontally apart from each other, rather than being disposed on the same vertical axis. At least one intermediate electrode, which electrically connects the at least one variable resistance region and the at least one switching device, may be between the at least one variable resistance region and the at least one switching device.

Abstract: The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.

Abstract: A stacked structure including a soluble organic semiconductor material and a water soluble photosensitive material is provided. The water soluble photosensitive material is disposed on the surface of the soluble organic semiconductor material.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: Resistance-switching oxide films, and devices therewith, are disclosed. Resistance-switching oxide films, according to certain preferred aspects of the present invention, include at least about 75 atomic percent of an insulator oxide matrix having a conducting material dopant in an amount up to about 25 atomic percent. The matrix and dopant are preferably in solid solution. The insulator oxide matrix may also preferably include about 6 to about 12 atomic percent of a conducting material dopant. According to certain aspects of the present invention, the insulator oxide matrix, the conducting material dopant, or both, may have a perovskite crystal structure. The insulator oxide matrix may preferably include at least one of LaAlO3 and CaZrO3. Preferred conducting material dopants include SrRuO3, CaRuO3, or combinations thereof.

Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

Abstract: Oxide semiconductors and thin film transistors (TFTs) including the same are provided. An oxide semiconductor includes Zn atoms and at least one of Hf and Cr atoms added thereto. A thin film transistor (TFT) includes a channel including an oxide semiconductor including Zn atoms and at least one of Hf and Cr atoms added thereto.

Abstract: An array substrate for a fringe field switching mode liquid crystal display device comprises a gate line on a substrate; a gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode; a semiconductor layer on the gate insulating layer and corresponding to the gate electrode; source and drain electrodes on the semiconductor layer and spaced apart from each other, the source electrode having first and second sub-source layers, the drain electrode having first and second sub-drain layers. Also disclosed in a method of fabricating a fringe field switching mode liquid crystal display device.

Abstract: To provide a display device capable of reliably forming a resistive element formed on a substrate including pixels. A display device including at least a thin-film transistor and a resistive element on a substrate has a gate electrode, an insulating film, a semiconductor layer and a conductive layer which are sequentially stacked on the substrate, in which the resistive element is formed by using the semiconductor layer formed between end portions of wiring made of the conductive layer as a resistive body, and at least one conductive layer apart from the end portions is formed on the semiconductor layer between the end portions of wiring.

Abstract: Provided is a thin film transistor that includes a substrate on which an insulating layer is formed, a gate formed on a region of the insulating layer, a gate insulating layer formed on the insulating layer and the gate, a channel region formed on the gate insulating layer on a region corresponding to the location of the gate, a source and a drain respectively formed by contacting either side of the channel region; and a passivation layer formed of a compound made of a group II element and a halogen element on the channel region.

Abstract: A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing.

Abstract: A vertical laminated electrical switch circuit includes a first, second, and third ceramic substrate positioned in juxtaposed relationship relative to each other. The circuit also includes a first and second electrical device electrically coupled to each other. The first electrical device is coupled to the first and second substrates and positioned there between. The second electrical device is coupled to the second and third ceramic substrates and positioned there between. In some embodiments, multiple electrical devices may be coupled to a single substrate.

Abstract: A method is provided for modifying a circuit containing a plurality of electrodes, within a substrate, comprising the steps of: (a) selecting at least two electrodes for making a connection; (b) removing materials covering the electrodes with a focused ion beam (FIB) or a laser to form contact holes for respectively exposing the electrodes; (c) depositing in the contact holes a conductive material for forming electrically conductive piers, by applying the focused ion beam (FIB) or laser, with gas molecules ejected from a nozzle; (d) disposing an electrically conductive viscid material over each of the electrically conductive piers; and (e) disposing an electrically conductive bridge floor to connect with the electrically conductive viscid material to form an electrically conductive bridge.

Abstract: Object: To provide a semiconductor device using titanium dioxide as an active layer and a method for producing thereof. Means for Solving the Problems: The semiconductor device 10 according to the present invention includes TiO2 as an active layer thereof. The semiconductor device 10 according to the present invention includes a gate electrode 20, a TiO2 layer 12 which functions as a semiconductor active layer and forming a channel, a source electrode and a drain electrode being electrically connected to the TiO2 layer, and an insulating film formed between the gate electrode and the TiO2 layer. The TiO2 layer 12 may be a single crystal substrate including a Rutile or Anatase structure which has a step-terrace structure. The TiO2 layer 12 may be a vapor deposition film of TiO2. Further the present invention provides a method for producing the semiconductor device using titanium dioxide as the active layer.

Abstract: A preferred embodiment microcavity plasma device array of the invention includes a plurality of first metal circumferential metal electrodes that surround microcavities in the device. The first circumferential electrodes are buried in a metal oxide layer and surround the microcavities in a plane transverse to the microcavity axis, while being protected from plasma in the microcavities by the metal oxide. In embodiments of the invention, the circumferential electrodes can be connected in patterns. A second electrode(s) is arranged so as to be isolated from said first electrodes by said first metal oxide layer. In some embodiments, the second electrode(s) is in a second layer, and in other embodiments the second electrode(s) is also within the first metal oxide layer. A containing layer, e.g., a thin layer of glass, quartz, or plastic, seals the discharge medium (plasma) into the microcavities. In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes.

Abstract: It is an object to obtain a display device which has a thin film transistor using a semiconductor film, and in which initial failures are reduced, and a high-resolution display due to miniaturization of the thin film transistor is enabled. In a thin film transistor, a gate electrode 6 is formed above a polycrystalline semiconductor film 4 via a gate insulating film 5. A taper angle ?2 of a section of a pattern end portion of the polycrystalline semiconductor film 4 in a region where the polycrystalline semiconductor film 4 and the gate electrode 6 intersect with each other is smaller than a taper angle ?1 of the other region.

Abstract: Provided are a method of manufacturing a transparent N-doped p-type ZnO semiconductor layer using a surface chemical reaction between precursors containing elements constituting thin layers, and a thin film transistor (TFT) including the p-type ZnO semiconductor layer. The method includes the steps of: preparing a substrate and loading the substrate into a chamber; injecting a Zn precursor and an oxygen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the oxygen precursor using an atomic layer deposition (ALD) technique to form a ZnO thin layer on the substrate; and injecting a Zn precursor and an nitrogen precursor into the chamber, and causing a surface chemical reaction between the Zn precursor and the nitrogen precursor to form a doping layer on the ZnO thin layer.

Abstract: A zinc oxide (ZnO) group and method of forming the same are provided. The ZnO group diode may include a first electrode and a second electrode that are separated from each other, and an active layer formed of MxIn1-xZnO (wherein “M” is a Group III metal) between the first electrode and the second electrode. The first electrode may have a work function lower than the active layer. The second electrode may have a work function higher than the active layer.

Abstract: A process for manufacturing a semiconductor device, provides that a silicide layer is formed, an amorphous semiconductor layer is applied both to the silicide layer and to an open monocrystalline semiconductor region, adjacent to the silicide layer, and during a subsequent temperature treatment, the amorphous semiconductor layer is crystallized proceeding from the open, monocrystalline semiconductor region, acting as a crystallization nucleus, so that the silicide layer is covered at least partially by a crystallized, monocrystalline semiconductor layer.

Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Abstract: A semiconductor device in accordance with one embodiment of the present invention includes: a strained semiconductor layer formed on a substrate; and a strain measuring region, provided on the substrate, for measuring a strain of the semiconductor layer. The semiconductor device may further include: a reference information measuring region, provided on the substrate, for measuring reference information for evaluating the strain of the semiconductor layer.

Abstract: In a memory device and a method of forming a memory device, the device comprises a substrate, a first electrode extending in a vertical direction relative to the substrate, and a second electrode extending in a vertical direction relative to the substrate, the second electrode being spaced apart from the first electrode by a vertical gap. A third electrode is provided that extends in a vertical direction in the electrode gap, the third electrode being spaced apart from the first electrode by a first gap and the third electrode being spaced apart from the second electrode by a second gap, the third electrode being elastically deformable such that the third electrode deflects to be electrically coupled with the first electrode through the first gap in a first bent position and to be electrically coupled with the second electrode through the second gap in a second bent position, and to be isolated from the first electrode and the second electrode in a rest position.

Abstract: A semiconductor chip having a current source coupled between a first potential and an electrical node, a detection circuit having an input coupled to the electrical node, and a first active component coupled in series with the current source and further coupled between the electrical node and a second potential, wherein the first active component is coupled to the electrical node via a first conductive interconnect.

Abstract: A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

Abstract: A semiconductor device may include multiple fuses spaced at a same pitch from each other and a check pattern spaced a predetermined distance from one side of the fuses, where the check pattern has the same width, height, and pitch as the fuses, and the fuses may be formed of a conductive material that may be one of W, WSi, Al or Cu.

Abstract: A method for fabricating a Finfet device with body contacts and a device fabricated using the method are provided. In one example, a silicon-on-insulator substrate is provided. A T-shaped active region is defined in the silicon layer of the silicon-on-insulator substrate. A source region and a drain region form two ends of a cross bar of the T-shaped active region and a body contact region forms a leg of the T-shaped active region. A gate oxide layer is grown on the active region. A polysilicon layer is deposited overlying the gate oxide layer and patterned to form a gate, where an end of the gate partially overlies the body contact region to complete formation of a Finfet device with body contact.

Abstract: A semiconductor device includes a dielectric layer, a semiconductor layer provided above the dielectric layer, a gate dielectric layer provided above the semiconductor layer, a gate electrode provided above the gate dielectric layer, a source region and a drain region provided in the semiconductor layer, a body region other than the source region and the drain region in the semiconductor layer, and a body contact region that divides the source region in a plurality of areas and joins to the body region, wherein the body contact region is formed of a compound of a semiconductor of the semiconductor layer and a metal.