Amorphous Materials (epo) Patents (Class 257/E29.08)
  • Patent number: 8963166
    Abstract: Toward making available III nitride crystal substrates advantageously employed in light-emitting devices, and light-emitting devices incorporating the substrates, a III nitride crystal substrate has a major face whose surface area is not less than 10 cm2 and is characterized by: edge dislocations in the crystal being concentrated along propagation lines forming an angle of some 0° to 5° with a given {0001} plane of the crystal; screw dislocations in the crystal being concentrated along propagation lines forming an angle of some 45° to 60° with the given {0001} plane; and in a major-face principal region excluding the peripheral margin of the major face from its outer periphery to a 5 mm separation from its outer periphery, the total dislocation density being between 1×104 cm?2 to 3×106 cm?2 inclusive, and the ratio of screw-dislocation density to the total dislocation density being 0.5 or greater.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: February 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shinsuke Fujiwara, Hiroaki Yoshida
  • Patent number: 8962457
    Abstract: A transistor comprises an active layer of an oxide containing at least one element selected from In, Ga and Zn. The active layer is formed such that a desorption gas monitored as a water molecule by a temperature programmed desorption analysis is 1.4/nm3 or less.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Watanabe
  • Patent number: 8963151
    Abstract: A high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Hoon Lee, Ki Se Kim
  • Patent number: 8431927
    Abstract: A thin film transistor including: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode and exposed portions of the substrate; an oxide semiconductor layer formed on the gate insulating layer to correspond to the gate electrode, and comprising an HfInZnO-based oxide semiconductor, wherein the concentration of Hf is from about 9 to about 15 at % based on 100 at % of the total concentration of Hf, In, and Zn; and source and drain regions respectively formed to extend on both sides of the oxide semiconductor layer and the gate insulating layer.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 30, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Suk Kim, Jin-Seong Park
  • Publication number: 20120305915
    Abstract: A method for fabricating a field-effect transistor having a gate electrode, a source electrode, a drain electrode, and an active layer forming a channel region, the active layer having an oxide semiconductor mainly containing magnesium and indium is disclosed. The method includes a deposition step of depositing an oxide film, a patterning step of patterning the oxide film by processes including etching to obtain the active layer, and a heat-treatment step of heat-treating the obtained active layer subsequent to the patterning step.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Applicant: RICOH COMPANY, LTD.
    Inventors: Yukiko Abe, Naoyuki Ueda, Yuki Nakamura, Yuji Sone
  • Patent number: 8319217
    Abstract: A thin film transistor including: a substrate; a gate electrode formed on the substrate; a gate insulating layer formed on the gate electrode and exposed portions of the substrate; an oxide semiconductor layer formed on the gate insulating layer to correspond to the gate electrode, and comprising an HfInZnO-based oxide semiconductor, wherein the oxide semiconductor layer has a Zn concentration gradient; and source and drain regions respectively formed on both sides of the oxide semiconductor layer and the gate insulating layer.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 27, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Suk Kim, Min-Kyu Kim
  • Publication number: 20120292617
    Abstract: An oxide sintered body including indium oxide of which the crystal structure substantially includes a bixbyite structure, wherein gallium atoms are solid-saluted in the indium oxide, and an atomic ratio Ga/(Ga+In) is 0.10 to 0.15.
    Type: Application
    Filed: January 14, 2011
    Publication date: November 22, 2012
    Inventors: Kazuaki Ebata, Shigekazu Tomai, Koki Yano
  • Publication number: 20120286266
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideomi SUZAWA, Shinya SASAGAWA, Taiga MURAOKA, Shunichi ITO, Miyuki HOSOBA
  • Publication number: 20120280233
    Abstract: A high efficiency heterostructure field effect transistor (HFET) capable of suppressing a leakage current and enhancing a current density by lowering a barrier between an electrode and a semiconductor layer is provided. The high efficiency HFET may include a substrate, a semi-insulating gallium nitride (GaN) layer formed on the substrate, an aluminum gallium nitride (AlGaN) layer formed on the GaN layer, and a silicon carbide (SixC1-x) functional layer formed on the AlGaN layer.
    Type: Application
    Filed: September 6, 2011
    Publication date: November 8, 2012
    Inventors: Jae Hoon LEE, Ki Se Kim
  • Patent number: 8253134
    Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-il Kim, Jae-cheol Lee, I-hun Song, Young-soo Park, Chang-jung Kim, Jae-chul Park
  • Patent number: 8183659
    Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 22, 2012
    Inventor: Mohammad Shafiqul Kabir
  • Patent number: 8148707
    Abstract: A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: April 3, 2012
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stanford Ovshinsky, Tyler Lowrey, James D. Reed, Semyon D. Savransky, Jason S. Reid, Kuo-Wei Chang
  • Publication number: 20120012838
    Abstract: A switching element of LCDs or organic EL displays which uses a thin film transistor device, includes: a drain electrode, a source electrode, a channel layer contacting the drain electrode and the source electrode, wherein the channel layer comprises indium-gallium-zinc oxide having a transparent, amorphous state of a composition equivalent to InGaO3(ZnO)m (wherein m is a natural number less than 6) in a crystallized state, and the channel layer has a semi-insulating property represented by an electron mobility of more than 1 cm2/(V·sec) and an electron carrier concentration is less than 1018/cm3, a gate electrode, and a gate insulating film positioned between the gate electrode and the channel layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 19, 2012
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hideo Hosono, Masahiro Hirano, Hiromichi Ota, Toshio Kamiya, Kenji Nomura
  • Patent number: 8058645
    Abstract: A thin film transistor (TFT), including a substrate, a gate electrode on the substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain electrodes in contact with the source and drain regions of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer has a GaInZnO (GIZO) bilayer structure including a lower layer and an upper layer, and the upper layer has a different indium (In) concentration than the lower layer.
    Type: Grant
    Filed: April 1, 2009
    Date of Patent: November 15, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jong-Han Jeong, Jae-Kyeong Jeong, Yeon-Gon Mo, Hui-Won Yang
  • Publication number: 20110260157
    Abstract: A semiconductor device, a thin film transistor, and a method for producing the same capable of decreasing the management cost, and capable of decreasing the production steps to reduce the production cost are proposed. A method for producing a thin film transistor 2 provided with a semiconductor which is composed of a prescribed material and serves as an active layer 41 and a conductor which is composed of a material having the same composition as that of the prescribed material and serves as at least one of a source electrode 51, a drain electrode 53 and a pixel electrode 55, which includes the steps of simultaneously forming into a film an object to be processed and a conductor (a source electrode 51, a source wire 52, a drain electrode 53, a drain wire 54 and a pixel electrode 55) which are composed of the amorphous prescribed material, followed by simultaneous shaping, and crystallizing the object to be processed which has been shaped to allow it to be the active layer 41.
    Type: Application
    Filed: May 1, 2008
    Publication date: October 27, 2011
    Inventors: Koki Yano, Kazuyoshi Inoue, Futoshi Utsuno, Masashi Kasami, Katsunori Honda
  • Patent number: 8013340
    Abstract: A semiconductor device includes a semiconductor body with a front-sided surface. An active cell region with a semiconductor device structure and an edge region surrounding the active cell region are arranged in the semiconductor body. The front-sided surface of the semiconductor body includes a passivation layer over the edge region and over the active cell region. The passivation layer includes a semiconducting insulation layer of a semiconducting material, the bandgap of which is greater than the bandgap of the material of the semiconductor body.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: September 6, 2011
    Assignee: Infineon Technologies AG
    Inventor: Gerhard Schmidt
  • Patent number: 7998372
    Abstract: Disclosed is a semiconductor thin film which can be formed at a relatively low temperature even on a flexible resin substrate. Since the semiconductor thin film is stable to visible light and has high device characteristics such as transistor characteristics, in the case where the semiconductor thin film is used as a switching device for driving a display, even when overlapped with a pixel part, the luminance of a display panel does not deteriorate. Specifically, a transparent semiconductor thin film 40 is produced by forming an amorphous film containing zinc oxide and indium oxide and then oxidizing the film so that the resulting film has a carrier density of 10+17 cm?3 or less, a Hall mobility of 2 cm2/V·sec or higher, and an energy band gap of 2.4 EV or more.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: August 16, 2011
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue, Nobuo Tanaka, Tokie Tanaka, legal representative
  • Publication number: 20110068336
    Abstract: An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 24, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Akiharu MIYANAGA, Masayuki SAKAKURA, Junichi KOEZUKA, Tetsunori MARUYAMA, Yuki IMOTO
  • Publication number: 20110068852
    Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 24, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Publication number: 20110049512
    Abstract: The invention provides a method for developing a thin film from oxide or silicate of hafnium nitride, and also provides asymmetric guanidinate coordinate compounds. The invention furthermore provides a method for producing an electronic circuit that includes a step for developing a thin film from oxide or silicate of hafnium nitride through the method of the invention.
    Type: Application
    Filed: March 16, 2009
    Publication date: March 3, 2011
    Inventors: Stéphane Daniele, Mohamad Eleter, Catherine Dubourdieu, Virginie Brize
  • Publication number: 20110042668
    Abstract: There is provided an amorphous oxide semiconductor material including an amorphous oxide semiconductor including In, Ga and Zn, wherein when In:Ga:Zn=a:b:c denotes an element composition ratio of the oxide semiconductor, the element composition ratio is defined by the range of a+b=2 and b<2 and c<4b?3.2 and c>?5b+8 and 1?c?2.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 24, 2011
    Applicant: FUJIFILM CORPORATION
    Inventors: Takeshi HAMA, Masayuki SUZUKI, Atsushi TANAKA, Fumihiko MOCHIZUKI
  • Publication number: 20110024741
    Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.
    Type: Application
    Filed: September 15, 2010
    Publication date: February 3, 2011
    Applicants: CANON KABUSHIKI KAISHA, TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Katsumi Abe, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7851792
    Abstract: Provided is a field-effect transistor including an active layer and a gate insulating film, wherein the active layer includes an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in the vicinity of or in contact with an interface between the amorphous oxide layer and the gate insulating film.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: December 14, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiaki Aiba, Masafumi Sano, Nobuyuki Kaji
  • Patent number: 7835177
    Abstract: A phase change memory (PCM) cell fabricated by etching a tapered structure into a phase change layer, and planarizing a dielectric layer on the phase change layer until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced, thereby lowering the operation current.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: November 16, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Hui Hsu, Chien-Min Lee, Wen-Han Wang, Min-Hung Lee, Te-Sheng Chao, Yen Chuo, Yi-Chan Chen, Wei-Su Chen
  • Publication number: 20100258794
    Abstract: A field effect transistor is provided including a gate electrode (15), a source electrode (13), a drain electrode (14) and a channel layer (11) to control current flowing between the source electrode (13) and the drain electrode (14) by applying a voltage to the gate electrode (15). The channel layer (11) is constituted of an amorphous oxide containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.
    Type: Application
    Filed: August 29, 2008
    Publication date: October 14, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tatsuya Iwasaki, Naho Itagaki
  • Patent number: 7812333
    Abstract: An integrated circuit includes a first electrode and a first resistivity changing material coupled to the first electrode. The first resistivity changing material has a planarized surface. The integrated circuit includes a second resistivity changing material contacting the planarized surface of the first resistivity changing material and a second electrode coupled to the second resistivity changing material. A cross-sectional width of the first resistivity changing material is less than a cross-sectional width of the second resistivity changing material.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: October 12, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Jan Boris Philipp, Thomas Happ
  • Patent number: 7777291
    Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir
  • Publication number: 20100163860
    Abstract: Disclosed is a semiconductor thin film which can be formed at a relatively low temperature even on a flexible resin substrate. Since the semiconductor thin film is stable to visible light and has high device characteristics such as transistor characteristics, in the case where the semiconductor thin film is used as a switching device for driving a display, even when overlapped with a pixel part, the luminance of a display panel does not deteriorate. Specifically, a transparent semiconductor thin film 40 is produced by forming an amorphous film containing zinc oxide and indium oxide and then oxidizing the film so that the resulting film has a carrier density of 10+17 cm?3 or less, a Hall mobility of 2 cm2/V·sec or higher, and an energy band gap of 2.4 EV or more.
    Type: Application
    Filed: November 16, 2006
    Publication date: July 1, 2010
    Inventors: Koki Yano, Kazuyoshi Inoue, Nobuo Tanaka, Tokie Tanaka
  • Patent number: 7700936
    Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 20, 2010
    Assignee: University of Delaware
    Inventors: Janusz Murakowski, Garrett Schneider, Dennis W. Prather
  • Patent number: 7663137
    Abstract: A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second electrode is over the metal-chalcogenide layer. The memory element is configured to have reduced current requirements.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 16, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Publication number: 20090278122
    Abstract: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6, a drain electrode 5, a gate electrode 4, a gate insulating film 3, and a channel layer 2, an amorphous oxide having an electron carrier concentration less than 1018/cm3 is used in the channel layer 2.
    Type: Application
    Filed: July 16, 2009
    Publication date: November 12, 2009
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hideo HOSONO, Masahiro HIRANO, Hiromichi OTA, Toshio KAMIYA, Kenji NOMURA
  • Publication number: 20090267064
    Abstract: The present invention provides a semiconductor thin film which can be manufactured at a relatively low temperature even on a flexible resin substrate. As a semiconductor thin film having a low carrier concentration, a high Hall mobility and a large energy band gap, an amorphous film containing zinc oxide and tin oxide is formed to obtain a carrier density of 10+17 cm?3 or less, a Hall mobility of 2 cm2/V·sec or higher, and an energy band gap of 2.4 eV or more. Then, the amorphous film is oxidized to form a transparent semiconductor thin film 40.
    Type: Application
    Filed: October 16, 2006
    Publication date: October 29, 2009
    Inventors: Koki Yano, Kazuyoshi Inoue, Nobuo Tanaka, Tokie Tanaka
  • Publication number: 20090194767
    Abstract: A method for producing a conductive oxide-deposited substrate including depositing a conductive oxide thin film over a substrate, subjecting the conductive oxide thin film to heat treatment by irradiating with a condensed laser beam so as to be thermally changed in part, and subjecting the conductive oxide thin film to etching treatment so as to remove a part which has not been thermally changed, wherein the conductive oxide thin film absorbs the laser beam, and at least a part of the conductive oxide thin film is an amorphous phase.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 6, 2009
    Inventors: Hiroshi MIURA, Kohji Takeuchi, Nobuaki Toyoshima
  • Patent number: 7482621
    Abstract: A bistable electrical device that is convertible between a low resistance state and a high resistance state. The device includes at least one layer of organic low conductivity material that is sandwiched between two electrodes. A buffer layer is located between the organic layer and at least one of the electrodes. The buffer layer includes particles in the form of flakes or dots of a low conducting material or insulating material that are present in a sufficient amount to only partially cover the electrode surface. The presence of the buffer layer controls metal migration into the organic layer when voltage pulses are applied between the electrodes to convert the device back and forth between the low and high resistance states.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 27, 2009
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, Liping Ma
  • Patent number: 7420246
    Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 2, 2008
    Assignee: DENSO CORPORATION
    Inventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
  • Publication number: 20080197338
    Abstract: Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a metal plug. The invention can mitigate keyholes in the contacts by capping and encapsulating the conductive material used to form the contact. The exemplary cap may be made of a nitride material.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 21, 2008
    Inventor: Jun Liu
  • Patent number: 7391050
    Abstract: A memory device is described an active material configured to be placed in a more or less conductive state by means of appropriate switching processes. The active material is positioned between a material having low thermal conductivity or material layers having low thermal conductivity.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Infineon Technologies AG
    Inventor: Thomas Happ
  • Patent number: 7332735
    Abstract: A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second electrode is over the metal-chalcogenide layer. The memory element is configured to have reduced current requirements.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: February 19, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kristy A. Campbell
  • Patent number: 7145172
    Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: December 5, 2006
    Assignee: Hannstar Display Corporation
    Inventors: Chih-Yu Peng, Wei-Chuan Lin, Chian-Chih Hsiao, Ta-Ko Chuang, Chun-Hung Chu, Chih-Lung Lin, Chin-Mao Lin