Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer.

Abstract: The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.

Abstract: An oxide including indium (In), gallium (Ga) and zinc (Zn), wherein diffraction peaks are observed at positions corresponding to incident angles (2?) of 7.0° to 8.4°, 30.6° to 32.0°, 33.8° to 35.8°, 53.5° to 56.5° and 56.5° to 59.5° in an X-ray diffraction measurement (CuK? rays), and one of diffraction peaks observed at positions corresponding to incident angles (2?) of 30.6° to 32.0° and 33.8° to 35.8° is a main peak and the other is a sub peak.

Abstract: An object of the present invention is to provide a novel semiconductor device which is excellent in stability, uniformity, reproducibility, heat resistance, durability and the like, and can exert excellent transistor properties. The semiconductor device is a thin-film transistor, and this thin-film transistor uses, as an active layer, a polycrystalline oxide semiconductor thin film containing In and two or more metals other than In and having an electron carrier concentration of less than 1×1018/cm3.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic % and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract: Provided is a connecting part for a semiconductor device including a semiconductor element, a frame, and a connecting part which connects the semiconductor element and the frame to each other, in which an interface between the connecting part and the semiconductor element and an interface between the connecting part and the frame respectively have the area of Al oxide film which is more than 0% and less than 5% of entire area of the respective interfaces. The connecting part has an Al-based layer and first and second Zn-based layers on main surfaces of the Al-based layer, a thickness ratio of the Al-based layer relative to the Zn-based layers being less than 0.59.

Abstract: An object is to prevent an impurity such as moisture and oxygen from being mixed into an oxide semiconductor and suppress variation in semiconductor characteristics of a semiconductor device in which an oxide semiconductor is used. Another object is to provide a semiconductor device with high reliability. A gate insulating film provided over a substrate having an insulating surface, a source and a drain electrode which are provided over the gate insulating film, a first oxide semiconductor layer provided over the source electrode and the drain electrode, and a source and a drain region which are provided between the source electrode and the drain electrode and the first oxide semiconductor layer are provided. A barrier film is provided in contact with the first oxide semiconductor layer.

Abstract: Methods of forming copper indium gallium diselenide (CIGS) layers for photovoltaic devices are disclosed. In one aspect, a solution based selenization method in the formation of CIGS is provided. In some embodiments a substrate containing elemental copper (Cu), indium (In) and gallium (Ga) is coated with a solution comprising a source of selenium (Se) dissolved in a solvent. After coating with the selenium based solution, the substrate is heated to form the CIGS layer. Coating of the substrate with the selenium based solution may be carried out by dip coating, slit casting, gap coating, ink-jet type coating, among other techniques. The solution based selenization method disclosed herein provides high material utilization and low cost, unlike vacuum based processes.

Abstract: An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.

Abstract: An object is to suppress occurrence of oxygen deficiency. An oxide semiconductor film is formed using germanium (Ge) instead of part of or all of gallium (Ga) or tin (Sn). At least one of bonds between a germanium (Ge) atom and oxygen (O) atoms has a bond energy higher than at least one of bonds between a tin (Sn) atom and oxygen (O) atoms or a gallium (Ga) atom and oxygen (O) atoms. Thus, a crystal of an oxide semiconductor formed using germanium (Ge) has a low possibility of occurrence of oxygen deficiency. Accordingly, an oxide semiconductor film is formed using germanium (Ge) in order to suppress occurrence of oxygen deficiency.

Abstract: The invention provides a thin film transistor comprising an active layer, the active layer comprising an IGZO-based oxide material, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153 and being formed from a single phase of IGZO having a crystal structure of YbFe2O4, and a method of producing the thin film transistor.

Abstract: Provided is a method of producing a circuit board of which the aperture ratio is increased. The method of producing a circuit board of the present invention is a method of producing a circuit board that includes a thin film transistor, the thin film transistor including an oxide semiconductor layer, the method including steps of: forming the oxide semiconductor layer; and converting the oxide semiconductor layer into a conductive form.

Abstract: A semiconductor wafer includes a base wafer, a first crystal layer, a second crystal layer and a third crystal layer. The first crystal layer has a first surface having a same orientation as the base wafer, and a second surface having a different orientation from the first surface, the second crystal layer has a third surface having the same orientation as the first surface, and a fourth surface having the same orientation as the second surface, the third crystal layer is in contact with a part of the third surface and the fourth surface. A thickness ratio of the second crystal layer in a region adjoining the first surface to a region adjoining the second surface is larger than a thickness ratio of the third crystal layer in a region adjoining the third surface to a region adjoining the fourth surface.

Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.

Abstract: This invention discloses a solution-based synthesis of cesium tin tri-iodide (CsSnI3) film. More specifically, the invention is directed to a solution-based drop-coating synthesis of cesium tin tri-iodide (CsSnI3) films. CsSnI3 films are ideally suited for a wide range of applications such as light emitting and photovoltaic devices.

Abstract: A method and apparatus for obtaining inspection information is described. A standard CCD or CMOS camera is used to obtain images in the near infrared region. Background and noise components of the obtained image are removed and the signal to noise ratio is increased to provide information that is suitable for use in inspection.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: A method is provided for growing a stable p-type ZnO thin film with low resistivity and high mobility. The method includes providing an n-type Li—Ni co-doped ZnO target in a chamber, providing a substrate in the chamber, and ablating the target to form the thin film on the substrate.

Abstract: Methods and devices are provided for forming multi-nary semiconductor. In one embodiment, a method is provided comprising of depositing a precursor material onto a substrate, wherein the precursor material may include or may be used with an additive to minimize concentration of group IIIA material such as Ga in the back portion of the final semiconductor layer. The additive may be a non-copper Group IB additive in elemental or alloy form. Some embodiments may use both selenium and sulfur, forming a senary or higher semiconductor alloy.

Abstract: An object of the present invention is to provide a novel semiconductor device which is excellent in stability, uniformity, reproducibility, heat resistance, durability and the like, and can exert excellent transistor properties. The semiconductor device is a thin-film transistor, and this thin-film transistor uses, as an active layer, a polycrystalline oxide semiconductor thin film containing In and two or more metals other than In and having an electron carrier concentration of less than 1×1018/cm3.

Abstract: A field effect transistor is provided including a gate electrode (for example, 15), a source electrode (13), a drain electrode (14) and a channel layer (11) to control current flowing between the source electrode (13) and the drain electrode (14) by applying a voltage to the gate electrode (15). The channel layer (11) is constituted of an amorphous oxide containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

Abstract: A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Abstract: Provided are an aqueous solution composition for fluorine doped metal oxide semiconductor, a method for manufacturing a fluorine doped metal oxide semiconductor using the same, and a thin film transistor including the same. The aqueous solution composition for fluorine doped metal oxide semiconductor includes: a fluorine compound precursor made of one or two or more selected from the group consisting of a metal compound containing fluorine and an organic material containing fluorine; and an aqueous solution containing water or catalyst. The method for manufacturing a fluorine doped metal oxide semiconductor, includes: preparing an aqueous solution composition for fluorine doped metal oxide semiconductor, coating a substrate with the aqueous solution composition; and performing heat treatment on the coated substrate to form the fluorine doped metal oxide semiconductor.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: A composition for preventing cracking in composite structures comprising a metal coated substrate and a selenide, sulfide or mixed selenidesulfide film. Specifically, cracking is prevented in the coating of molybdenum coated substrates upon which a copper, indium-gallium diselenide (CIGS) film is deposited. Cracking is inhibited by adding a Se passivating amount of oxygen to the Mo and limiting the amount of Se deposited on the Mo coating.

Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.

Abstract: In formation of a quantum dot structure in a light emitting layer, a matrix region (an n-type conductive layer and matrix layers) is formed on a growth underlying layer of AlN whose abundance ratio of Al is higher (or whose lattice constant is smaller) than that in the matrix region by an MBE technique, thereby to realize conditions where compression stress is caused in an in-plane direction perpendicular to the direction of growth of the matrix region, and then to form island crystals by self-organization in the presence of this compression stress. The compression stress inhibits an increase in lattice constant caused by the reduced abundance ratio of Al in the matrix region, i.e., to compensate for a difference in lattice constant between the island crystals and the matrix region. The compression stress functions to enlarge compositional limits for formation of the island crystals by self-organization to the Ga-rich side.

Abstract: Provided is a method for manufacturing a low-cost bonded wafer (8) which allows bulk crystals of a wide bandgap semiconductor (1) to be transferred onto a handle substrate (3) as thinly as possible without breaking the substrate. More specifically, provided is a method for manufacturing a bonded wafer (8) by forming a wide bandgap semiconductor film (4) on a surface of a handle substrate (3), the method comprising a step of implanting ions from a surface (5) of a wide bandgap semiconductor substrate (1) having a bandgap of 2.8 eV or more to form an ion-implanted layer (2), a step of applying a surface activation treatment to at least one of the surface of the handle substrate (3) and the ion-implanted surface (5) of the wide bandgap semiconductor substrate (1), a step of bonding the surface (5) of the wide bandgap semiconductor substrate (1) and the surface of the handle substrate (3) to obtain bonded substrates (6), a step of applying a heat treatment to the bonded substrates (6) at a temperature of 150° C.

Abstract: A thin film transistor according to the present invention includes: a semiconductor layer (5); a source electrode (3s) and a drain electrode (3d) that each are connected to the semiconductor layer (5); an insulating layer (6) that is formed adjacent to the semiconductor layer (5); and a gate electrode (7) that faces the semiconductor layer (5) across the insulating layer (6). The semiconductor layer (5) includes an aggregate of semiconductor fine particles composed of a complex oxide. The complex oxide contains zinc and at least one selected from a group consisting of indium, gallium and rhodium.

Abstract: A multilayer film stack containing germanium, antimony and tellurium that can be annealed to form a GST product material of homogeneous and smooth character, wherein at least one antimony-containing layer is isolated from a tellurium-containing layer by an intervening germanium layer, and the multilayer film stack comprises at least two intervening germanium layers. The multilayer film stack can be formed by vapor deposition techniques such as chemical vapor deposition or atomic layer deposition. The annealable multilayer film stack can be formed in high aspect ratio vias to form phase change memory devices of superior character with respect to the stoichiometric and morphological characteristics of the GST product material.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

Abstract: The present invention generally relates to nanotechnology and, in particular, to branched nanoscale wires cases, the branched nanoscale wires may be produced using vapor-phase and/or solution-phase synthesis. Branched nanoscale wires may be grown by depositing nanoparticles onto a nanoscale wire, and segments or “branches” can then be grown from the nanoparticles. The nanoscale wire may be any nanoscale wire, for example, a semiconductor nanoscale wire, a nanoscale wire having a core and a shell. The segments may be of the same, or of different materials, than the nanoscale wire, for example, semiconductor/metal, semiconductor/semiconductor. The junction between the segment and the nanoscale wire, in some cases, is epitaxial. In one embodiment, the nanoparticles are adsorbed onto the nanoscale wire by immobilizing a positively-charged entity, such as polylysine, to the nanoscale wire, and exposing it to the nanoparticles.

Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.

Abstract: On a nitride semiconductor layered portion formed on a substrate, there are formed an insulating film and a p-side electrode in this order. Furthermore, an end portion electrode protection layer is formed above the p-side electrode, around a position where cleavage will take place.

Abstract: An oxide semiconductor thin-film transistor, comprising: a source electrode and a drain electrode formed on a substrate; a composite semiconductor active layer formed between the source electrode and the drain electrode; a gate dielectric layer formed on the source electrode, the composite semiconductor active layer and the drain electrode; and a gate electrode formed on the gate dielectric layer and corresponding to the composite semiconductor active layer; wherein the composite semiconductor active layer comprises a low carrier-concentration first oxide semiconductor layer and a high carrier-concentration second oxide semiconductor layer.

Abstract: Semiconductor devices having at least one barrier layer with a wide energy band gap are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. The at least one barrier layer may have a wider energy band gap than an energy band gap of the at least one active layer. The compositions of the first and second compounds may be controlled to adjust the difference between Fermi functions for conduction band and valence band in the at least one active layer.

Abstract: A field effect transistor is provided including a gate electrode (15), a source electrode (13), a drain electrode (14) and a channel layer (11) to control current flowing between the source electrode (13) and the drain electrode (14) by applying a voltage to the gate electrode (15). The channel layer (11) is constituted of an amorphous oxide containing In and Si and having a compositional ratio expressed by Si/(In+Si) of not less than 0.05 and not more than 0.40.

Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

Abstract: Provided are a thin film transistor, to which a boron-doped oxide semiconductor thin film is applied as a channel layer, and a method of fabricating the same. The thin film transistor includes source and drain electrodes, a channel layer, a gate insulating layer, and a gate electrode, which are formed on a substrate. The channel layer is an oxide semiconductor thin film doped with boron. Therefore, it is possible to remarkably improve electrical characteristics and high temperature stability of the thin film transistor.

Abstract: An object is to prevent an impurity such as moisture and oxygen from being mixed into an oxide semiconductor and suppress variation in semiconductor characteristics of a semiconductor device in which an oxide semiconductor is used. Another object is to provide a semiconductor device with high reliability. A gate insulating film provided over a substrate having an insulating surface, a source and a drain electrode which are provided over the gate insulating film, a first oxide semiconductor layer provided over the source electrode and the drain electrode, and a source and a drain region which are provided between the source electrode and the drain electrode and the first oxide semiconductor layer are provided. A barrier film is provided in contact with the first oxide semiconductor layer.

Abstract: In one embodiment, a method of producing an optoelectronic nanostructure includes preparing a substrate; providing a quantum well layer on the substrate; etching a volume of the substrate to produce a photonic crystal. The quantum dots are produced at multiple intersections of the quantum well layer within the photonic crystal. Multiple quantum well layers may also be provided so as to form multiple vertically aligned quantum dots. In another embodiment, an optoelectronic nanostructure includes a photonic crystal having a plurality of voids and interconnecting veins; a plurality of quantum dots arranged between the plurality of voids, wherein an electrical connection is provided to one or more of the plurality of quantum dots through an associated interconnecting vein.

Abstract: Devices and methods of fabrication of ZnO based single and multi-junction photovoltaic cells are disclosed. ZnO based single and multijunction photovoltaic cells, and other optoelectronic devices include p-type, n-type, and undoped materials of ZnxA1-xOyB1-y, wherein the alloy composition A and B, expressed by x and y, respectively, varies between 0 and 1. Alloy element A is selected from related elements including Mg, Be, Ca, Sr, Cd, and In and alloy element B is selected from a related elements including Te and Se. The selection of A, B, x and y, allows tuning of the material's band gap. The band gap of the material may be selected to range between approximately 1.4 eV and approximately 6.0 eV. ZnxA1-xOyB1-y based tunnel diodes may be formed and employed in ZnxA1-xOyB1-y based multi-junction photovoltaic devices. ZnxA1-xOyB1-y based single and multi-junction photovoltaic devices may also include transparent, conductive heterostructures and highly doped contacts to ZnO based substrates.

Abstract: An oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may be obtained by adding hafnium (Hf) to gallium-indium-zinc oxide (GIZO) and may be used as a channel material of the TFT.

Abstract: In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including In, Ga, and Zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced. Three layers of a gate insulating film, an oxide semiconductor layer and a channel protective layer are successively formed by a sputtering method without being exposed to air. Further, in the oxide semiconductor layer, the thickness of a region overlapping with the channel protective film is larger than that of a region in contact with a conductive film.

Abstract: Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

Abstract: Methods and compositions for depositing a metal containing film on a substrate are disclosed. A reactor and at least one substrate disposed in the reactor are provided. A metal containing precursor is provided and introduced into the reactor, which is maintained at a temperature of at least 100° C. A metal is deposited on to the substrate through a deposition process to form a thin film on the substrate.

Abstract: An electrochemical deposition method to form uniform and continuous Group IIIA material rich thin films with repeatability is provided. Such thin films are used in fabrication of semiconductor and electronic devices such as thin film solar cells. In one embodiment, the Group IIIA material rich thin film is deposited on an interlayer that includes 20-90 molar percent of at least one of In and Ga and at least 10 molar percent of an additive material including one of Cu, Se, Te, Ag and S. The thickness of the interlayer is adapted to be less than or equal to about 20% of the thickness of the Group IIIA material rich thin film.

Abstract: A method of dividing single crystals, particularly of plates of parts thereof, is proposed, which can comprise: pre-adjusting the crystallographic cleavage plane (2?) relative to the cleavage device, setting a tensional intensity (K) by means of tensional fields (3?, 4?), determining an energy release rate G(?) in dependence from a possible deflection angle (?) from the cleavage plane (2?) upon crack propagation, controlling the tensional fields (3?, 4?) such that the crack further propagates in the single crystal, wherein G(0)?2?e(0) and simultaneously at least one of the following conditions is satisfied: ? ? G ? ? ? ? = 0 ? 2 ? ? e h ? ? if ? ? ? 2 ? G ? ? 2 ? 0 ? ? or ( 2.1 ) ? ? G ? ? ? ? 2 ? ? e h ? ? ? ? : ? ? 1 < ? < ? 2 , ( 2.