Amorphous Materials (epo) Patents (Class 257/E29.092)
  • Patent number: 8884346
    Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8829482
    Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Antonio R. Gallo, Chakravarthy Gopalan, Yi Ma
  • Publication number: 20130088468
    Abstract: A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 11, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: SEMICONDUCTOR ENERGY LABORATORY CO.
  • Publication number: 20130069072
    Abstract: A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.
    Type: Application
    Filed: July 20, 2012
    Publication date: March 21, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Shuichi TOMABECHI
  • Publication number: 20120261655
    Abstract: Inorganic semiconducting compounds, composites and compositions thereof, and related device structures.
    Type: Application
    Filed: January 16, 2012
    Publication date: October 18, 2012
    Applicant: Northwestern University
    Inventors: Tobin J. Marks, Antonio Facchetti, Lian Wang, Myung-Han Yoon, Yu Yang
  • Patent number: 8253178
    Abstract: An example complementary metal oxide semiconductor (CMOS) image sensor includes an epitaxial layer, an array of pixels, and a trench capacitor. The array of pixels are formed on a front side of the epitaxial layer in an pixel array area of the image sensor. The array of pixels includes one or more shallow trench isolation structures disposed between adjacent pixels for isolating the pixels in the pixel array area. The trench capacitor is formed on the front side of the epitaxial layer in a peripheral circuitry area of the image sensor.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: August 28, 2012
    Assignee: OmniVision Technologies, Inc.
    Inventors: Rongsheng Yang, Zhiqiang Lin
  • Patent number: 8237166
    Abstract: An active matrix display comprising a light control device and a field effect transistor for driving the light control device. The active layer of the field effect transistor comprises an amorphous.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: August 7, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Hideya Kumomi, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 8212252
    Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 3, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Tohru Den, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 8203146
    Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 19, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Katsumi Abe, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Publication number: 20120146184
    Abstract: A memcapacitor device includes a memcapacitive matrix interposed between a first electrode and a second electrode. The memcapacitive matrix includes deep level dopants having a first decay time constant and shallow level dopants having a second decay time constant. The second decay time constant is substantially shorter than the first decay time constant. The capacitance of the memcapacitor device depends upon an initial voltage applied across the memcapacitive matrix and a time dependent change in capacitance of the memcapacitor device depends upon the first decay time constant. A method for forming a memcapacitive device is also provided.
    Type: Application
    Filed: August 28, 2009
    Publication date: June 14, 2012
    Inventors: Matthew Pickett, Julien Borghetti, Jianhua Yang
  • Patent number: 8168974
    Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 1, 2012
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Masafumi Sano, Katsumi Nakagawa, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Publication number: 20110168993
    Abstract: Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.
    Type: Application
    Filed: June 11, 2010
    Publication date: July 14, 2011
    Inventors: Sang-hun Jeon, I-hun Song, Chang-jung Kim, Sung-ho Park
  • Patent number: 7872259
    Abstract: An object of the present invention is to provide a new light-emitting device with the use of an amorphous oxide. The light-emitting device has a light-emitting layer existing between first and second electrodes and a field effect transistor, of which the active layer is an amorphous.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 18, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Tohru Den, Tatsuya Iwasaki, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7868326
    Abstract: A novel field-effect transistor is provided which employs an amorphous oxide. In an embodiment of the present invention, the transistor comprises an amorphous oxide layer containing electron carrier at a concentration less than 1×10?18/cm3, and the gate-insulating layer is comprised of a first layer being in contact with the amorphous oxide and a second layer different from the first layer.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 11, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Masafumi Sano, Katsumi Nakagawa, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7863611
    Abstract: Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 1018/cm3 is used for the N-type region.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: January 4, 2011
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Katsumi Abe, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7791072
    Abstract: An active matrix display comprising a light control device and a field effect transistor for driving the light control device. The active layer of the field effect transistor comprises an amorphous.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: September 7, 2010
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Hideya Kumomi, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Patent number: 7692177
    Abstract: A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin metal containing layer having a thickness of less than about 250 Angstroms over a second chalcogenide glass layer, formed over a first metal containing layer, formed over a first chalcogenide glass layer. The thin metal containing layer preferably is a silver layer. An electrode may be formed over the thin silver layer. The electrode preferably does not contain silver.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: April 6, 2010
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Kristy A. Campbell, Terry L. Gilton
  • Publication number: 20090072290
    Abstract: An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
    Type: Application
    Filed: September 19, 2007
    Publication date: March 19, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Louis C. Hsu, Jack A. Mandelman, William Tonti
  • Patent number: 7129512
    Abstract: The present invention provides a semiconductor laser device including a heat sink having one main surface, an n-AlGaAs cladding layer disposed on the main surface of the heat sink, an AlGaAs active layer disposed on the n-AlGaAs cladding layer and a p-AlGaAs cladding layer disposed on the AlGaAs active layer. An effective refractive index and a thermal resistance between a main surface on the heat sink side, of the AlGaAs active layer and a main surface on the heat sink side, of the n-AlGaAs cladding layer are respectively set smaller than those between a main surface on the side opposite to the heat sink, of the AlGaAs active layer and a main surface on the side opposite to the heat sink, of the p-AlGaAs cladding layer.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: October 31, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kimio Shigihara