Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

Abstract: A method of growing large GaAs or GaP IR window slabs by HVPE, and in embodiments by LP-HVPE, includes obtaining a plurality of thin, single crystal, epitaxial-quality GaAs or GaP wafers, cleaving the wafers into tiles having ultra-flat, atomically smooth, substantially perpendicular edges, and then butting the tiles together to form an HVPE substrate larger than 4 inches for GaP, and larger than 8 inches or even 12 inches for GaAs. Subsequent HVPE growth causes the individual tiles to fuse by optical bonding into a large “tiled” single crystal wafer, while any defects nucleated at the tile boundaries are healed, causing the tiles to merge with themselves and with the slab with no physical boundaries, and no degradation in optical quality. A dopant such as Si can be added to the epitaxial gases during the final HVPE growth stage to produce EMI shielded GaAs windows.

Abstract: A nitride-based semiconductor device includes a substrate, a buffer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a S/D electrode, a second S/D electrode, and a gate electrode. The buffer is disposed over the substrate and includes at least one layer of a nitride-based semiconductor compound doped with an acceptor at a top-most portion of the buffer. The first and second nitride-based semiconductor layers are disposed over the buffer. The first S/D electrode is disposed over the second nitride-based semiconductor layer, in which the first S/D electrode extends downward to a position lower than the first nitride-based semiconductor layer, so as to form at least one first interface with the top-most portion of the buffer, making contact with the at least one layer of the nitride-based semiconductor compound. The second S/D electrode and the gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).

Abstract: Embodiments of the present application disclose a semiconductor structure and a manufacturing method for the semiconductor structure, which solve problems of complicated manufacturing process and poor stability and reliability of existing semiconductor structures. The semiconductor structure includes: a substrate; a channel layer, a barrier layer and a semiconductor layer sequentially superimposed on the substrate, wherein the semiconductor layer is made of a GaN-based material and an upper surface of the semiconductor layer is Ga-face; and a p-type GaN-based semiconductor layer, with N-face as an upper surface, formed in a gate region of the semiconductor layer.

Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.

Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Abstract: There is provided a method for producing a nitride semiconductor laminate in which a thin film is homoepitaxially grown on a substrate comprising group III nitride semiconductor crystals, the method including: homoepitaxially growing a thin film on a substrate, using the substrate in which a dislocation density on its main surface is 5×106 pieces/cm2 or less, a concentration of oxygen therein is less than 1×1017 at·cm?3, and a concentration of impurities therein other than n-type impurity is less than 1×1017 at ·cm?3; and inspecting a film quality of the thin film formed on the substrate, wherein in the inspection of the film quality, the film quality of the thin film is inspected by detecting a deviation of an amount of reflected light at a predetermined wavenumber determined in a range of 1,600 cm?1 or more and 1,700 cm?1 or less in a reflection spectrum obtained by irradiating the thin film on the substrate with infrared light, from an amount of reflected light at the predetermined wavenumber determined ac

Abstract: The present invention provides a vertical-type thin film transistor (TFT). The vertical TFT may comprise a source electrode and a drain electrode extending parallel to each other, with a semiconductor layer arranged in between the source electrode and the drain electrode. A single gate electrode may be embedded in the semiconductor layer, the single gate electrode comprising micro-perforations configured to control the flow of electrons therethrough in dependence on a predetermined voltage difference between the source electrode and the single gate electrode. The gate electrode masks a direct electric field between the source electrode and the drain electrode. A rate of flow of electrons through the perforations is increased with an increase in the predetermined voltage.

Abstract: A semiconductor structure and a manufacturing method therefor are provided by embodiments of the present application. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. In the second buffer layer, by decreasing a doping concentration of the transition metal or not doping intentionally the transition metal, a tailing effect is avoided and current collapse is prevented. By doping periodically C in the buffer layer, C may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced.

Abstract: A semiconductor device includes a semiconductor part including a first semiconductor layer of a first conductivity type; a first electrode provided on a back surface of the semiconductor part; and a second electrode provided on a front surface of the semiconductor part. The second electrode includes a barrier layer and a metal layer. The barrier layer contacts the first semiconductor layer and including vanadium or a vanadium compound as a major component. The metal layer is provided on the barrier layer.

Abstract: Light emitting devices employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge carrier sheet within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening material layer between two III-N material layers. Where a light emitting structure includes a quantum well (QW) structure between two Group III-Nitride polarization junctions, a 2D electron gas (2DEG) induced at a first polarization junction and/or a 2D hole gas (2DHG) induced at a second polarization junction on either side of the QW structure may supply carriers to the QW structure. An improvement in quantum efficiency may be achieved where the intervening material layer further functions as a barrier to carrier recombination outside of the QW structure.

Abstract: A method of manufacturing a light-emitting element includes: providing a semiconductor structure including: a first layer containing gallium and nitrogen, a second layer of a first conductive type, the second layer containing gallium, aluminum, and nitrogen and being located on or above the first layer, an active layer located on or above the second layer, and a third layer of a second conductive type, the third layer located on or above the active layer, wherein a thickness of the first layer is larger than a thickness of the second layer; performing chemical-mechanical polishing from a first layer side to reduce the thickness of the first layer; and performing dry etching from the first layer side to remove the first layer and reduce the thickness of the second layer.

Abstract: A biological chip, a manufacturing method thereof, an operation method thereof, and a biological detection system are provided. The biological chip includes a base substrate and a plurality of working units. The plurality of the working units are arranged on the base substrate; each of the working units includes a working element configured to be in contact with a target substance; and the working element includes a metal electrode and an electric-field-controllable surface modification layer on a surface of the metal electrode.

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed.

Abstract: A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.

Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.

Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.

Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

Abstract: A semiconductor device includes first and second conductive layers over an insulating surface, a first insulating layer over the first and second conductive layers, first and second oxide semiconductor layers over the first insulating layer, third and fourth conductive layers over the first oxide semiconductor layer, a second insulating layer over the third and fourth conductive layers, and a fifth conductive layer over the second insulating layer. In the semiconductor device, the third conductive layer is electrically connected to the second conductive layer, the fifth conductive layer is electrically connected to the fourth conductive layer, the first oxide semiconductor layer has a region overlapping with the first conductive layer, the second oxide semiconductor layer has a region overlapping with the fifth conductive layer, and the second oxide semiconductor layer has a region intersecting with the second conductive layer.

Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.

Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.

Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.

Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.

Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

Abstract: Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a light emitting layer disposed between a n-type semiconductor layer and a p-type semiconductor layer, and a hole supply layer disposed between the light emitting layer and the p-type semiconductor layer. The hole supply layer is made from material InxGa1-xN (0<x<1) and is doped with a Group IV-A element at a concentration ranging from 1017 to 1020 cm?3. By being doped with the Group IV-A element, the concentration of holes is increased and inactivation caused by Mg—H bonds is reduced. Thus Mg is activated as acceptors and the light emitting efficiency is further increased.

Abstract: The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 ?m or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired.

Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.

Abstract: Methods of fabrication of electronic modules comprise, on the one hand, power electronic components fabricated on a substrate made of gallium nitride (GaN) and, on the other hand, micro-switches using electrostatic activation of the MEMS (Micro Electro Mechanical System) type. The electronic components and the micro-switches are fabricated on a single gallium nitride substrate and the fabrication method comprises at least the following steps: fabrication of the power components on the gallium nitride substrate; deposition of a first common passivation layer on said components and on the substrate; fabrication of the micro-switches on said substrate.

Abstract: To provide a light emitting element, having: a lamination structure including a first conductive layer and a second conductive layer with a light emitting layer interposed between them; a groove structure in which the second conductive layer and the light emitting layer are divided into large and small two parts; a second conductive electrode pad that is electrically connected to the second conductive layer on the divided larger second conductive layer, a first conductive electrode pad on the divided smaller second conductive layer, and two or more electrical contacts connected to the first conductive layer so as to be independent from each other, by a conductive wiring extending to the first conductive layer, with the first conductive electrode pad as a start point.

Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.

Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.

Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.

Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.