Only Group Iii-v Compounds (epo) Patents (Class 257/E29.089)
  • Patent number: 9041187
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 26, 2015
    Assignee: International Rectifier Corporation
    Inventor: Martin Standing
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8987833
    Abstract: In one implementation, a stacked composite device comprises a group IV lateral transistor and a group III-V transistor stacked over the group IV lateral transistor. A drain of the group IV lateral transistor is in contact with a source of the group III-V transistor, a source of the group IV lateral transistor is coupled to a gate of the group III-V transistor to provide a composite source on a top side of the stacked composite device, and a drain of the group III-V transistor provides a composite drain on the top side of the stacked composite device. A gate of the group IV lateral transistor provides a composite gate on the top side of the stacked composite device, and a substrate of the group IV lateral transistor is on a bottom side of the stacked composite device.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Tim McDonald, Michael A. Briere
  • Patent number: 8975165
    Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 10, 2015
    Assignee: Soitec
    Inventors: Christophe Figuet, Ed Lindow, Pierre Tomasini
  • Patent number: 8969180
    Abstract: A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Hui Nie, Andrew P. Edwards, Donald R. Disney, Richard J. Brown, Isik C. Kizilyalli
  • Patent number: 8963164
    Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Sanae Shimizu, Kenji Imanishi, Atsushi Yamada, Toyoo Miyajima
  • Patent number: 8956935
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoko Kurahashi
  • Patent number: 8952494
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: February 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Patent number: 8927999
    Abstract: An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 6, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8927985
    Abstract: A semiconductor device includes first and second conductive layers over an insulating surface, a first insulating layer over the first and second conductive layers, first and second oxide semiconductor layers over the first insulating layer, third and fourth conductive layers over the first oxide semiconductor layer, a second insulating layer over the third and fourth conductive layers, and a fifth conductive layer over the second insulating layer. In the semiconductor device, the third conductive layer is electrically connected to the second conductive layer, the fifth conductive layer is electrically connected to the fourth conductive layer, the first oxide semiconductor layer has a region overlapping with the first conductive layer, the second oxide semiconductor layer has a region overlapping with the fifth conductive layer, and the second oxide semiconductor layer has a region intersecting with the second conductive layer.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideki Matsukura
  • Patent number: 8928000
    Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8912079
    Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: December 16, 2014
    Assignees: The University of Tokyo, V Technology Co., Ltd.
    Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
  • Patent number: 8912081
    Abstract: The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: December 16, 2014
    Assignee: SOITEC
    Inventor: Bruce Faure
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8895337
    Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Patent number: 8896100
    Abstract: A III nitride structure includes a film 108 having a surface composed of a metal formed in a predetermined region on the surface of a substrate 102, and a fine columnar crystal 110 composed of at least a III nitride semiconductor formed on the surface of the substrate 102, wherein the spatial occupancy ratio of the fine columnar crystal 110 is higher on the surface of the substrate 102 where the film 108 is not formed than that on the film.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: November 25, 2014
    Assignee: Sophia School Corporation
    Inventors: Katsumi Kishino, Akihiko Kikuchi
  • Patent number: 8883548
    Abstract: Electronic device quality Aluminum Antimonide (AlSb)-based single crystals produced by controlled atmospheric annealing are utilized in various configurations for solar cell applications. Like that of a GaAs-based solar cell devices, the AlSb-based solar cell devices as disclosed herein provides direct conversion of solar energy to electrical power.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 11, 2014
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: John W. Sherohman, Jick Hong Yee, Arthur W. Combs, III
  • Patent number: 8884307
    Abstract: According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm?3 or more and less than 1×1021 cm?3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hung Hung, Tomonari Shioda, Jongil Hwang, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8884308
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8872187
    Abstract: The invention relates to a membrane. Partly permeable membranes often have holes or perforations having a specific diameter to allow substances having a smaller particle diameter to pass through, but to hold back substances having a larger particle diameter. Such membranes are subject to wear primarily at the holes, i.e. cracks form which grow through the membrane proceeding from a hole. Particularly in the case of micromechanical membranes having holes having a small diameter in the range of 1 ?m or less, it is very difficult to detect the state of the membrane, in particular whether the latter has cracks. Membranes having cracks can then undesirably allow passage even of those particles which should actually be held back. In medical or hygienic applications, the function can then be impaired.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: October 28, 2014
    Assignee: Airbus Operations GmbH
    Inventors: Alois Friedberger, Andreas Helwig, Gerhard Mueller
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8872157
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a light emitting layer disposed between a n-type semiconductor layer and a p-type semiconductor layer, and a hole supply layer disposed between the light emitting layer and the p-type semiconductor layer. The hole supply layer is made from material InxGa1-xN (0<x<1) and is doped with a Group IV-A element at a concentration ranging from 1017 to 1020 cm?3. By being doped with the Group IV-A element, the concentration of holes is increased and inactivation caused by Mg—H bonds is reduced. Thus Mg is activated as acceptors and the light emitting efficiency is further increased.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Genesis Photonics Inc.
    Inventors: Jyun-De Wu, Yu-Chu Li
  • Patent number: 8871556
    Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: October 28, 2014
    Assignee: Kyma Technologies, Inc.
    Inventors: Edward Preble, Lianghong Liu, Andrew D. Hanser, N. Mark Williams, Xueping Xu
  • Patent number: 8859318
    Abstract: Methods of fabrication of electronic modules comprise, on the one hand, power electronic components fabricated on a substrate made of gallium nitride (GaN) and, on the other hand, micro-switches using electrostatic activation of the MEMS (Micro Electro Mechanical System) type. The electronic components and the micro-switches are fabricated on a single gallium nitride substrate and the fabrication method comprises at least the following steps: fabrication of the power components on the gallium nitride substrate; deposition of a first common passivation layer on said components and on the substrate; fabrication of the micro-switches on said substrate.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: October 14, 2014
    Assignee: Thales
    Inventors: Afshin Ziaei, Matthieu Le Baillif
  • Patent number: 8860294
    Abstract: To provide a light emitting element, having: a lamination structure including a first conductive layer and a second conductive layer with a light emitting layer interposed between them; a groove structure in which the second conductive layer and the light emitting layer are divided into large and small two parts; a second conductive electrode pad that is electrically connected to the second conductive layer on the divided larger second conductive layer, a first conductive electrode pad on the divided smaller second conductive layer, and two or more electrical contacts connected to the first conductive layer so as to be independent from each other, by a conductive wiring extending to the first conductive layer, with the first conductive electrode pad as a start point.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: October 14, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tatsunori Toyota, Yutaka Ohta
  • Patent number: 8853744
    Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Michael A. Briere
  • Patent number: 8853745
    Abstract: A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: October 7, 2014
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Jeffrey R. LaRoche, Valery S. Kaper, John P. Bettencourt, Kelly P. Ip
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 8836081
    Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 16, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8835985
    Abstract: According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
  • Patent number: 8828849
    Abstract: A method of producing single-crystal semiconductor material comprises: providing a template material; creating a mask on top of the template material; using the mask to form a plurality of nanostructures in the template material; and growing the single-crystal semiconductor material onto the nanostructures.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: September 9, 2014
    Assignee: Nanogan Limited
    Inventor: Wang Nang Wang
  • Patent number: 8822311
    Abstract: A III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 2, 2014
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Richard J. Brown, Donald R. Disney
  • Patent number: 8823013
    Abstract: A Schottky contact is disposed atop the surface of the semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and joins the first Schottky contact metal layer. A first. Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 2, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Ting Gang Zhu, Marek Pabisz
  • Patent number: 8809868
    Abstract: Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×1017 cm?3, and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 19, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yohei Enya, Takashi Kyono, Takamichi Sumitomo, Yusuke Yoshizumi, Koji Nishizuka
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8785942
    Abstract: A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse. In a nitride semiconductor substrate 10 having a substrate 1, a buffer layer 2 formed on one principal plane of the substrate 1, an intermediate layer 3 formed on the buffer layer 2, an electron transport layer 4 formed on the intermediate layer 3, and an electron supply layer 5 formed on the electron transport layer 4, the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5×1016 atoms/cm3 to 1×1018 atoms/cm3 and is of AlxGa1-xN (0.05?x?0.24), and the electron transport layer 4 has a thickness of 5 nm to 200 nm and is of AlyGa1-yN (0?y?0.04).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 22, 2014
    Assignee: Covalent Materials Corporation
    Inventors: Akira Yoshida, Jun Komiyama, Yoshihisa Abe, Hiroshi Oishi, Kenichi Eriguchi, Shunichi Suzuki
  • Patent number: 8785943
    Abstract: According to one embodiment, a nitride semiconductor device includes a foundation layer, a first stacked intermediate layer, and a functional layer. The foundation layer includes an AlN buffer layer formed on a substrate. The first stacked intermediate layer is provided on the foundation layer. The first stacked intermediate layer includes a first AlN intermediate layer provided on the foundation layer, a first AlGaN intermediate layer provided on the first AlN intermediate layer, and a first GaN intermediate layer provided on the first AlGaN intermediate layer. The functional layer is provided on the first stacked intermediate layer. The first AlGaN intermediate layer includes a first step layer in contact with the first AlN intermediate layer. An Al composition ratio in the first step layer decreases stepwise in a stacking direction from the first AlN intermediate layer toward the first step layer.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8785973
    Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 22, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Vladislav Vashchenko
  • Patent number: 8772077
    Abstract: The present invention concerns a method of forming a chalcogenide thin film for a phase-change memory. In the method of forming a chalcogenide thin film according to the present invention, a substrate with a pattern formed is loaded into a reactor, and a source gas is supplied onto the substrate. Here, the source gas includes at least one source gas selected from germanium (Ge) source gas, gallium (Ga) source gas, indium (In) source gas, selenium (Se) source gas, antimony (Sb) source gas, tellurium (Te) source gas, tin (Sn) source gas, silver (Ag) source gas, and sulfur (S) source gas. A first purge gas is supplied onto the substrate in order to purge the source gas supplied onto the substrate, a reaction gas for reducing the source gas is then supplied onto the substrate, and a second purge gas is supplied onto the substrate in order to purge the reaction gas supplied onto the substrate.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: July 8, 2014
    Assignee: IPS Ltd.
    Inventors: Ki-Hoon Lee, Jung-Wook Lee, Dong-Ho You
  • Patent number: 8766275
    Abstract: This composite semiconductor device has a normally-on first field effect transistor and a normally-off second field effect transistor connected in series between first and second terminals, gates of the first and second field effect transistors being connected to second and third terminals, respectively, and N diodes being connected in series in a forward direction between a drain and a source of the second field effect transistor. Therefore, a drain-source voltage (Vds) of the second field effect transistor can be restricted to a voltage not higher than a withstand voltage of the second field effect transistor.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: July 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Naoyasu Iketani, Tomohiro Nozawa, Yoshiaki Nozaki, John K. Twynam, Hiroshi Kawamura, Keiichi Sakuno
  • Patent number: 8759837
    Abstract: A nitride semiconductor substrate is featured in comprising: a GaN semiconductor layer grown on a base layer, which has a substantially triangular cross-section along the thickness direction thereof, a periodic stripe shapes, and uneven surfaces arranged on the stripes inclined surfaces; and an overgrown layer composed of AlGaN or InAlGaN on the GaN semiconductor layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: June 24, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Harumasa Yoshida, Yasufumi Takagi, Masakazu Kuwabara
  • Patent number: 8754430
    Abstract: A light emitting device is disclosed. The light emitting device includes a first conductive type semiconductor layer, an active layer disposed on the first conductive type semiconductor layer, a tunnel junction layer comprising a second conductive type nitride semiconductor layer and a first conductive type nitride semiconductor layer disposed on the active layer, wherein the first conductive type nitride semiconductor layer and the second conductive type nitride semiconductor layer are PN junctioned, a first electrode disposed on the first conductive type semiconductor layer, and a second electrode disposed on the first conductive type nitride semiconductor layer, wherein a portion of the second electrode is in schottky contact with the second conductive type nitride semiconductor layer through the first conductive type nitride semiconductor layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 17, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jae Hoon Kim
  • Patent number: 8748940
    Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
  • Patent number: 8741707
    Abstract: A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 3, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Isik C. Kizilyalli, Linda Romano, Andrew Edwards, Hui Nie
  • Patent number: 8736025
    Abstract: An object of the present invention is to address the problems described herein and to provide a III-nitride semiconductor epitaxial substrate, a III-nitride semiconductor element, and a III-nitride semiconductor freestanding substrate, which have good crystallinity, not only with AlGaN, GaN, or GaInN, the growth temperature of which is at or below 1050° C., but also with AlxGa1-xN, the growth temperature of which is high and which has a high Al composition, as well as a III-nitride semiconductor growth substrate for fabricating these and a method for efficiently fabricating these. The invention is characterized by being equipped with: a crystal growth substrate, at least the surface portion of which substrate includes a III-nitride semiconductor containing Al; and a single metallic layer formed on the surface portion, the single metallic layer being made from Zr or Hf.
    Type: Grant
    Filed: December 25, 2009
    Date of Patent: May 27, 2014
    Assignees: Dowa Electroncs Materials Co., Ltd., Dowa Holdings Co., Ltd.
    Inventors: Ryuichi Toba, Masahito Miyashita, Tatsunori Toyota
  • Patent number: 8729604
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 20, 2014
    Assignee: Fujitsu Limited
    Inventor: Naoko Kurahashi
  • Patent number: 8729672
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 20, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8728234
    Abstract: The present invention discloses methods to create higher quality group III-nitride wafers that then generate improvements in the crystalline properties of ingots produced by ammonothermal growth from an initial defective seed. By obtaining future seeds from carefully chosen regions of an ingot produced on a bowed seed crystal, future ingot crystalline properties can be improved. Specifically, the future seeds are optimized if chosen from an area of relieved stress on a cracked ingot or from a carefully chosen N-polar compressed area. When the seeds are sliced out, miscut of 3-10° helps to improve structural quality of successive growth. Additionally a method is proposed to improve crystal quality by using the ammonothermal method to produce a series of ingots, each using a specifically oriented seed from the previous ingot. When employed, these methods enhance the quality of Group III nitride wafers and thus improve the efficiency of any subsequent device.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: May 20, 2014
    Assignee: Sixpoint Materials, Inc.
    Inventors: Edward Letts, Tadao Hashimoto, Masanori Ikari
  • Patent number: 8723185
    Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai, Ho-Yung David Hwang
  • Patent number: 8723222
    Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 13, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung Bum Bae, Eun Soo Nam, Jae Kyoung Mun, Sung Bock Kim, Hae Cheon Kim, Chull Won Ju, Sang Choon Ko, Jong-Won Lim, Ho Kyun Ahn, Woo Jin Chang, Young Rak Park