Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

Abstract: A silicon carbide semiconductor switching device having a planar metal oxide semiconductor insulated gate structure. The silicon carbide semiconductor switching device includes a silicon carbide semiconductor substrate having a bandgap wider than that of silicon, a drift layer formed on the silicon carbide semiconductor substrate, a base region selectively formed in the drift layer at a top surface thereof, a source contact region selectively formed in the base region at a top surface thereof, a trench formed in the drift layer at the top surface thereof, the trench having a depth that is shallower than a depth of the source contact region, a gate electrode embedded in the trench, a top surface of the gate electrode being substantially flush with a top surface of the source contact region, and an interlayer insulating film formed on the top surfaces of the source contact region and the gate electrode.

Abstract: An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region.

Abstract: A transistor used for a semiconductor device for high power application needs to have a channel region for obtaining higher drain current. As an example of such a transistor, a vertical (trench type) transistor has been considered; however, the vertical transistor cannot have a high on/off ratio of drain current and thus cannot have favorable transistor characteristics. Over a substrate having conductivity, an oxide semiconductor layer having a surface having a dotted pattern of a plurality of island-shaped regions with a tapered shape in a cross section is sandwiched between a first electrode formed between the substrate and the oxide semiconductor layer and a second electrode formed over the oxide semiconductor layer, and a conductive layer functioning as a gate electrode is formed on the side surface of the island-shaped region in the oxide semiconductor layer with an insulating layer provided therebetween.

Abstract: Semiconductor devices having strong excitonic binding are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. An energy band gap of the at least one barrier layer is wider than energy band gap of the at least one active layer, and the first and/or second compounds are selected to strengthen an excitonic binding between an electron and a hole in the at least one active layer.

Abstract: Disclosed is an interconnection structure which, in a display device such as an organic EL display and a liquid crystal display, is capable of stably connecting a semiconductor layer directly to an Al-base film constituting, for example, a source electrode or a drain electrode; and which hardly causes galvanic corrosion between the semiconductor layer and the Al-base film in an electrolyte solution to be used in a wet process and is able to suppress stripping of the Al-base film. It is an interconnection structure including a semiconductor layer of a thin-film transistor and an Al alloy film connected directly to the semiconductor layer above a substrate in this order from the side of the substrate, wherein the semiconductor layer is composed of an oxide semiconductor, and the Al alloy film contains at least one of Ni and Co.

Abstract: Implementations and techniques for semiconductor light-emitting devices including one or more copper blend I-VII compound semiconductor material barrier layers are generally disclosed.

Abstract: Semiconductor devices having strong excitonic binding are disclosed. In some embodiments, a semiconductor device includes at least one active layer composed of a first compound, and at least one barrier layer composed of a second compound and disposed on at least one surface of the at least one active layer. An energy band gap of the at least one barrier layer is wider than energy band gap of the at least one active layer, and the first and/or second compounds are selected to strengthen an excitonic binding between an electron and a hole in the at least one active layer.

Abstract: A CaF2 buffer layer (3) is formed on a CaF2 (111) substrate (2) by an MBE method. Furthermore, a CuCl thin film is grown on the CaF2 buffer layer (3) by the MBE method while irradiating it with an electron beam to form an electro beam irradiation film (1a). Subsequently, a CuCl thin film is grown by the MBE method without the irradiation of electron beam to form an electron beam non-irradiation film (1b), thereby thus forming a CuCl thin film (a) including the electron beam irradiation film (1a) and the electron beam non-irradiation film (1b). Consequently, a CuCl thin film (1) exhibiting high planarity and crystallinity can be formed.

Abstract: A compliant substrate having a reduced stress, a method for manufacturing the same having a reduced manufacturing time, a gallium nitride based compound semiconductor device including the compliant substrate and a method for manufacturing the same are disclosed. The compliant substrate is manufactured by heating a substrate and a group III metal including at least one of an aluminum, a gallium and an indium, and a chloride based compound generated by introducing a HCl gas to the melted group III metal reacts with a NH3 gas to form a nitride based thin film on the wafer.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A thermionic or thermotunneling generator or heat pump is disclosed, comprising electrodes substantially facing one another and separated by spacers disposed between the electrodes, wherein the substrate material for the cathode is preferably a single crystalline silicon wafer while the substrate for the anode is an organic wafer, and preferably a polished polyimide (PI) wafer. On the cathode side, standard silicon wafer processes create the 10-1000 nm thin spacers and edge seals from thermally grown oxide. Either wafer is partially covered with a thin film of material that is characterized by high electrical conductivity and low work function. In one embodiment, the cathode is partially covered with a thin film of Ag—Cs—O. In another embodiment, the anode is additionally covered with a thin film of Ag—Cs—O, in which case the work function of the cathode coating material is reduced further utilizing an Avto Metal structure of nanoscale patterned indents.

Abstract: Disclosed is a method for fabricating a CuInS2 thin film by metal-organic chemical vapor deposition (MOCVD). The method comprises fabricating a copper thin film by depositing an asymmetric copper precursor on a substrate by MOCVD and fabricating a CuInS2 thin film by depositing an indium-sulfur-containing precursor on the copper thin film by MOCVD. The method enables fabrication of a CuInS2 thin film with a constant composition even under vacuum as well as an argon (Ar) atmosphere. Disclosed is further a CuInS2 thin film fabricated by the method. Disclosed is further a method for fabricating an In2S3 thin film for a window of a solar cell via deposition of an indium-sulfur-containing precursor on the CuInS2 thin film by MOCVD. Disclosed further is an In2S3 thin film fabricated by the method. The In2S3 thin film is useful for a substitute for CdS conventionally used for windows of solar cells and contributes to simplification in fabrication process of solar cells.