Abstract: An internal-ion gated electrochemical transistor is provided. In some embodiments, the internal-ion gated electrochemical transistor comprises: a gate electrode, a source electrode, and a drain electrode; a channel formed between the source electrode and the drain electrode, wherein the channel comprises a conducting polymer, wherein the channel serves as a reservoir of positively charged mobile ions; and an ion membrane between the channel and the gate electrode, wherein: in an off state, at least a subset of the positively charged mobile ions are ionically bonded to negatively charged ions of the conducting polymer, and wherein in an on state, at least a subset of the positively charged mobile ions are unbonded from the negatively charged ions of the conducting polymer to induce a current within the channel, and wherein at least one of the off state and the on state is actuated by application of a voltage to the gate electrode.

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

Abstract: Provided are a thin film transistor substrate which include a substrate, a buffer layer and a thin film transistor, a display apparatus including the thin film transistor substrate, and a method of manufacturing the display apparatus including the thin film transistor substrate. The buffer layer includes an inorganic insulating layer. An area ratio of a peak corresponding to an N—H bond in the buffer layer is 0.5% or less based on a total peak area in a Fourier transform infrared spectroscopy (FTIR).

Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.

Abstract: A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.

Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.

Abstract: The purpose of the invention is to form a stable oxide semiconductor TFT in a display device. The concrete structure is: A display device having a TFT substrate that includes a TFT having an oxide semiconductor layer comprising: the oxide semiconductor layer is formed on a first insulating film that is formed by a silicon oxide layer, the oxide semiconductor layer and an aluminum oxide film are directly formed on the first insulating film. The first insulating film becomes oxygen rich when the aluminum oxide film is formed on the first insulating film by sputtering. Oxygens in the first insulating film is effectively confined in the first insulating film, eventually, the oxygens diffuse to the oxide semiconductor for a stable operation of the oxide semiconductor TFT.

Abstract: A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.

Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.

Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.

Abstract: An IC device (100) includes an IC body (106) having a base layer (108) and first and second upper layers (114, 116) on the base layer. The IC body includes a cavity region (104) extending through said base and first upper layers and at least a portion of said second upper layer. In the IC device, a portion of said second upper layer in the cavity region comprises a planar inductive element (102) having first and second contacting ends (140, 142). In the IC device, at least one support member (128, 130, 132) extends at least partially into said cavity region from said IC body in at least a first direction parallel to said base layer and intersects at least a portion of said planar inductive element.

Abstract: A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc.

Abstract: An object is to provide a semiconductor device including a thin film transistor which includes an oxide semiconductor layer and has high electric characteristics. An oxide semiconductor layer including SiOx is used in a channel formation region, and in order to reduce contact resistance with source and drain electrode layers formed using a metal material with low electric resistance, source and drain regions are provided between the source and drain electrode layers and the oxide semiconductor layer including SiOx. The source and drain regions are formed using an oxide semiconductor layer which does not include SiOx or an oxynitride film.

Abstract: High temperature semiconducting materials in a freestanding epitaxial chip enables the use of high temperature interconnect and bonding materials. Process materials can be used which cure, fire, braze, or melt at temperatures greater than 400 degrees C. These include, but are not limited to, brazing alloys, laser welding, high-temperature ceramics and glasses. High temperature interconnect and bonding materials can additionally exhibit an index of refraction intermediate to that of the freestanding epitaxial chip and its surrounding matrix. High index, low melting point glasses provide a hermetic seal of the semiconductor device and also index match the freestanding epitaxial chip thereby increasing extraction efficiency. In this manner, a variety of organic free semiconducting devices, such as solid-sate lighting sources, can be created which exhibit superior life, efficiency, and environmental stability.

Abstract: Transistors and methods of manufacturing the same. A transistor may be an oxide thin film transistor (TFT) with a self-aligned top gate structure. The transistor may include a gate insulating layer between a channel region and a gate electrode that extends from two sides of the gate electrode. The gate insulating layer may cover at least a portion of source and drain regions.

Abstract: An IC device (100) includes an IC body (106) having a base layer (108) and first and second upper layers (114, 116) on the base layer. The IC body includes a cavity region (104) extending through said base and first upper layers and at least a portion of said second upper layer. In the IC device, a portion of said second upper layer in the cavity region comprises a planar inductive element (102) having first and second contacting ends (140, 142). In the IC device, at least one support member (128, 130, 132) extends at least partially into said cavity region from said IC body in at least a first direction parallel to said base layer and intersects at least a portion of said planar inductive element.

Abstract: Disclosed are an oxide semiconductor and a thin film transistor (TFT) including the same. The oxide semiconductor may include a lanthanoid (Ln) added to zinc oxide (ZnO) and may be used as a channel material of the TFT.

Abstract: Si(1-v-w-x)CwAlxNv crystals in a mixed crystal state are formed. A method for manufacturing an easily processable Si(1-v-w-x)CwAlxNv substrate, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer are provided. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer 12 (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate 11 by a pulsed laser deposition method.

Abstract: An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.

Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

Abstract: A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress.

Abstract: Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

Abstract: A transistor including an oxide semiconductor with favorable electric characteristics and a manufacturing method thereof are provided. A semiconductor device includes a transistor. The transistor includes an oxide semiconductor film over a base insulating film, a gate electrode overlapping with the oxide semiconductor film with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film and serving as a source electrode and a drain electrode. The base insulating film includes a first oxide insulating film partly in contact with the oxide semiconductor film and a second oxide insulating film in the periphery of the first oxide insulating film. An end portion of the oxide semiconductor film which crosses the channel width direction of the transistor is located over the second oxide insulating film.

Abstract: Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming three-dimensionally stacked cross point memory arrays. The method includes forming an insulating material over a first conductive electrode, patterning the insulating material to form vias that expose portions of the first conductive electrode, forming a memory access device within the vias of the insulating material and forming a memory element over the memory access device, wherein data stored in the memory element is accessible via the memory access device. The memory access device is formed of a doped chalcogenide material and formed using a self-aligned fabrication method.

Abstract: Disclosed herein is a thin-film transistor having a gate electrode; a source electrode and a drain electrode which form a source/drain-electrode pair; and a channel layer which is provided between the gate electrode and the source/drain-electrode pair, includes a poly-crystal oxide semiconductor material and has a film thickness smaller than the average diameter of crystal grains of the poly-crystal oxide semiconductor material.

Abstract: Disclosed herein are processes for making quaternary chalcogenide wafers. The process comprises milling quaternary chalcogenide crystals to form milled particles, and then compressing the milled particles to form a quaternary chalcogenide wafer. The quaternary chalcogenide wafers are useful for forming solar cells.

Abstract: Devices having a thin film or laminate structure comprising hafnium and/or zirconium oxy hydroxy compounds, and methods for making such devices, are disclosed. The hafnium and zirconium compounds can be doped, typically with other metals, such as lanthanum. Examples of electronic devices or components that can be made include, without limitation, insulators, transistors and capacitors. A method for patterning a device using the materials as positive or negative resists or as functional device components also is described. For example, a master plate for imprint lithography can be made. An embodiment of a method for making a device having a corrosion barrier also is described. Embodiments of an optical device comprising an optical substrate and coating also are described. Embodiments of a physical ruler also are disclosed, such as for accurately measuring dimensions using an electron microscope.

Abstract: The present method of forming a metal oxide film can increase production efficiency while maintaining the low resistance of the metal oxide film. The present method of forming a metal oxide film includes first misting a solution containing a metallic element and ethylenediamine; meanwhile, heating a substrate; and then, supplying the misted solution onto a first main surface of the substrate.

Abstract: In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is exposed to a functionalizing material that binds to carbon atoms in the graphene sheets so that the functionalizing material remains between the graphene sheets, thereby generating a functionalized graphitic structure. The functionalized graphitic structure is dried in an inert environment.

Abstract: A CMOS thin film transistor arrangement including a PMOS poly-silicon thin film transistor having a top gate configuration and a NMOS oxide thin film transistor having an inverted staggered bottom gate configuration where both transistors share the same gate electrode. The shared gate electrode is used as a doping or implantation mask in the formation of the source and drain regions of the poly-silicon transistor.

Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.

Abstract: A hetero pn junction semiconductor constituted of an electrically conductive polymer as a p-type semiconductor and an inorganic oxide as an n-type semiconductor, which is characterized in that the electrically conductive polymer is filled among nanoparticles of the inorganic oxide so as to satisfy the following Equation 1: Vp/Vn=X×?n/?p(0.

Abstract: The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number density of the forbidden band control element in the iron sulfide. An n-type semiconductor is manufactured by incorporating a group 13 element of the IUPAC system into iron sulfide. Moreover, a p-type semiconductor is manufactured by incorporating a group Ia element into iron sulfide. A semiconductor junction device or a photoelectric converter is manufactured by using the n-type semiconductor and the p-type semiconductor.

Abstract: The present invention relates to devices, particularly photovoltaic devices, incorporating Group IIB/VA semiconductors such phosphides, arsenides, and/or antimonides of one or more of Zn and/or Cd. In particular, the present invention relates to methodologies, resultant products, and precursors thereof in which electronic performance of the semiconductor material is improved by causing the Group IIB/VA semiconductor material to react with at least one metal-containing species (hereinafter co-reactive species) that is sufficiently co-reactive with at least one Group VA species incorporated into the Group IIB/VA semiconductor as a lattice substituent (recognizing that the same and/or another Group VA species also optionally may be incorporated into the Group IIB/VA semiconductor in other ways, e.g., as a dopant or the like).

Abstract: A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

Abstract: The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge1-ySny buffer layer on a semiconductor substrate and forming a tensile strained Ge layer on the Ge1-ySny buffer layer using an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between 1:10 and 1:30. The disclosure further provides semiconductor structures having highly strained Ge epilayers (e.g., between about 0.15% and 0.45%) as well as compositions comprising an admixture of (GeH3)2CH2 and Ge2H6 in a ratio of between about 1:10 and 1:30. The methods herein provide, and the semiconductor structure provide, Ge epilayers having high strain levels which can be useful in semiconductor devices for example, in optical fiber communications devices.

Abstract: In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: An electrochemical transistor comprising an electrolyte is disclosed. The electrolyte includes an ionic liquid. In a preferred embodiment, the transistor further comprises a source electrode, a drain electrode separated from the source electrode so as to form a gap between the source and drain electrodes, a semiconductor layer bridging the gap between the source and drain electrodes to form a transistor channel, and a gate electrode separated from the source electrode, the drain electrode and the semiconductor layer. In this embodiment, the electrolyte is disposed so as to contact at least a part of both the semiconductor layer and the gate electrode.

Abstract: An AlxGayIn1-x-yN crystal substrate of the present invention has a main plane having an area of at least 10 cm2. The main plane has an outer region located within 5 mm from an outer periphery of the main plane, and an inner region corresponding to a region other than the outer region. The inner region has a total dislocation density of at least 1×102 cm?2 and at most 1×106 cm?2. It is thereby possible to provide an AlxGayIn1-x-yN crystal substrate having a large size and a suitable dislocation density for serving as a substrate for a semiconductor device, a semiconductor device including the AlxGayIn1-x-yN crystal substrate, and a method of manufacturing the same.

Abstract: An object is, in a thin film transistor including an oxide semiconductor layer, to reduce contact resistance between the oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer. The source and drain electrode layers have a stacked-layer structure of two or more layers in which a layer in contact with the oxide semiconductor layer is formed using an oxide of a metal whose work function is lower than the work function of the oxide semiconductor layer or an oxide of an alloy containing such a metal. Layers other than the layer in contact with the oxide semiconductor layer of the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

Abstract: An object is, in a thin film transistor including an oxide semiconductor layer, to reduce contact resistance between the oxide semiconductor layer and source and drain electrode layers electrically connected to the oxide semiconductor layer. The source and drain electrode layers have a stacked-layer structure of two or more layers in which a layer in contact with the oxide semiconductor layer is formed using a metal whose work function is lower than the work function of the oxide semiconductor layer or an alloy containing such a metal. Layers other than the layer in contact with the oxide semiconductor layer of the source and drain electrode layers are formed using an element selected from Al, Cr, Cu, Ta, Ti, Mo, or W, an alloy containing any of these elements as a component, an alloy containing any of these elements in combination, or the like.

Abstract: A method for fabricating a multi-layer phase change memory device includes forming a phase change memory layer including a plurality of phase change memory elements on a word line formed on a plurality of semiconductor devices on a first semiconductor substrate, each phase change element having a notch formed at an upper surface thereof, forming an access device layer including plurality of access devices on a second semiconductor substrate, each access device having a conductive bump formed thereon, and combining the first and second semiconductor substrates and slidably inserting and locking each conductive bump of the plurality of access devices into each notch of the plurality of phase change memory elements to electrically connect the access devices to the phase change memory elements.

Abstract: A method for manufacturing a pixel structure includes providing a substrate including a transistor region and a pixel region, forming at least one gate electrode on the transistor region, forming an insulating layer on the substrate to overlay the gate electrode, and forming a patterned semi-conductive layer on the surface of a portion of the insulating layer disposed on the transistor region and the pixel region. A patterned first protective layer is formed on a portion of the patterned semi-conductive layer corresponding to the gate electrode, and the patterned semi-conductive layer is doped without being overlaid by the patterned first protective layer.

Abstract: An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide.

Abstract: A method of fabricating a semiconductor junction is disclosed. The method includes forming a quaternary heterovalent compound semiconductor alloy epilayer, determining a doping characteristic of the epilayer, and forming a secondary layer on the epilayer to create a semiconductor junction, the secondary layer being doped in response to the determined doping characteristic of the epilayer. Solar cell and light emitting diode designs are also disclosed.

Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.

Abstract: Si(1-v-w-x)CwAlxNv crystals in a mixed crystal state are formed. A method for manufacturing an easily processable Si(1-v-w-x)CwAlxNv substrate, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer are provided. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer 12 (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate 11 by a pulsed laser deposition method.

Abstract: Provided is a method of manufacturing a sensor structure, where vertically-well-aligned nanotubes are formed and the sensor structure having an excellent performance can be manufactured at the room temperature at low cost by using the nanotubes. The method of manufacturing a sensor structure includes: (a) forming a lower electrode on a substrate; (b) forming an organic template having a pore structure on the lower electrode; (c) forming a metal oxide thin film in the organic template; (d) forming a metal oxide nanotube structure, in which nanotubes are vertically aligned and upper portions thereof are connected to each other, by removing the organic template through a dry etching method; and (e) forming an upper electrode on the upper portions of the nanotubes.

Abstract: This invention relates to an electronic semiconductive component comprising at least one layer (2,3) of a p-type or n-type material, wherein the layer of a said p- or n-type material is constituted by a metal hydride having a chosen dopant. The invention also relates to methods for producing the component.