Characterized By Relative Position Of Source Or Drain Electrode And Gate Electrode (epo) Patents (Class 257/E29.122)
  • Patent number: 9029939
    Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8941175
    Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: January 27, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Lin Chen, Ke-Feng Lin, Chiu-Ling Lee, Chiu-Te Lee, Chih-Chung Wang, Hsuan-Po Liao
  • Patent number: 8921948
    Abstract: The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8901673
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Takamitsu Onda
  • Patent number: 8889510
    Abstract: A method for forming a surrounding stacked gate fin FET nonvolatile memory structure includes providing a silicon-on-insulator (SOI) substrate of a first conductivity type, patterning a fin active region on a region of the substrate, forming a tunnel oxide layer on the fin active region, and depositing a first gate electrode of a second conductivity type on the tunnel oxide layer and upper surface of the substrate. The method further includes forming a dielectric composite layer on the first gate electrode, depositing a second gate electrode on the dielectric composite layer, patterning the first and second gate electrodes to define a surrounding stacked gate area, forming a spacer layer on a sidewall of the stacked gate electrode, and forming elevated source/drain regions in the fin active region on both sides of the second gate electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 18, 2014
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: De Yuan Xiao, Lily Jiang, Gary Chen, Roger Lee
  • Patent number: 8816448
    Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Atsuhiro Kinoshita
  • Patent number: 8803248
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • Patent number: 8791456
    Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function ?ms of a source electrode in contact with the oxide semiconductor, the work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md. By electrically connecting a gate electrode and the drain electrode of the thin film transistor, a non-linear element with a more favorable rectification property can be achieved.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 29, 2014
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 8742492
    Abstract: A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum structure. The conical frustum structure includes a drain formed at a bottom portion of the conical frustum, a source formed at a top portion of the vertical conical frustum, and a channel formed at a middle portion of the conical frustum connecting the source and the drain. The GAA structure overlaps with the source at one side of the GAA structure, crosses over the channel, and overlaps with the drain at another side of the GAA structure.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hak-Lay Chuang, Ming Zhu, Yi-Ren Chen
  • Patent number: 8698234
    Abstract: A semiconductor device including a connecting structure includes an edge region, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: April 15, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Markus Zundel
  • Patent number: 8686528
    Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: April 1, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yudai Takanishi, Masao Moriguchi
  • Patent number: 8587037
    Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: November 19, 2013
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Tahir Hussain
  • Patent number: 8569837
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: October 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
  • Patent number: 8513716
    Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yoshitaka Ueda, Kouichi Yamada, Atsushi Wada, Shigeto Kobayashi
  • Patent number: 8492806
    Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function ?ms of a source electrode in contact with the oxide semiconductor, the work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md. By electrically connecting a gate electrode and the drain electrode of the thin film transistor, a non-linear element with a more favorable rectification property can be achieved.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Kawae
  • Patent number: 8390044
    Abstract: A non-linear element (such as a diode) which includes an oxide semiconductor and has a favorable rectification property is provided. In a transistor including an oxide semiconductor in which the hydrogen concentration is 5×1019/cm3 or lower, a work function ?ms of a source electrode in contact with the oxide semiconductor, a work function ?md of a drain electrode in contact with the oxide semiconductor, and electron affinity ? of the oxide semiconductor satisfy ?ms??<?md, and an area of contact between the drain electrode and the oxide semiconductor is larger than an area of contact between the source electrode and the oxide semiconductor. By electrically connecting a gate electrode and the drain electrode in the transistor, a non-linear element having a favorable rectification property can be achieved.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kawae, Hideki Uochi, Shunpei Yamazaki
  • Patent number: 8367491
    Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: February 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8362575
    Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Hsien-Hsin Lin
  • Patent number: 8294238
    Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Takayuki Toba, Yoshiko Kato, Kenji Gomikawa, Haruhiko Koyama
  • Patent number: 8269355
    Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: September 18, 2012
    Assignee: Linear Technology Corporation
    Inventor: David Alan Pruitt
  • Patent number: 8169029
    Abstract: A high voltage device with constant current source and the manufacturing method thereof. The device includes a P type silicon substrate (1), an oxide layer (6), a drain metal (2), a source metal (3), a gate metal (4), a P+substrate contact region (51), a N+drain region (52), an N+source region (53), an N?channel region (54) connecting the said N+drain region (52) and N+source region (53), and an N?drain region (92) enveloping the said N+drain region (52); the drain metal (2) fills drain through hole (82) and connects the N+drain region (52); the source metal (3) fills source through hole (83), and connects the N+source region (53) and P+substrate contact region (51); the source metal (3) and gate metal (4) are electrically connected by connecting metal (34). The manufacturing method includes steps of forming N+drain region, N+source region, N?drain region, P+substrate contact region, N?drain region and metal layer.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: May 1, 2012
    Assignee: Nanker (Guan Zhou) Semiconductor Manufacturing Corp.
    Inventor: Wei-Kuo Wu
  • Patent number: 8154088
    Abstract: Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: April 10, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Antoine Khoueir, Subhash Srinivas Pidaparthi, Henry Jim Fulford
  • Patent number: 8089575
    Abstract: A display device includes a sequentially stacked body formed of a gate signal line, an insulation film, a semiconductor layer and a conductor layer on a substrate. The conductive layer forms a drain electrode and a source electrode of a thin film transistor which are arranged with a channel region of the semiconductor layer therebetween, and one of the drain and source electrode is formed in an approximately U shape having an open-ended one end side and a connecting portion on another end side so that the one electrode surrounds a distal end portion of another electrode as viewed in a plan view, and a projecting portion is formed on a side of the connecting portion opposite to the another electrode.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: January 3, 2012
    Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Miyo Ishii, Junichi Uehara, Kunihiko Watanabe
  • Patent number: 8044460
    Abstract: A connecting structure for an electronic device includes an edge region of the device, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: October 25, 2011
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Markus Zundel
  • Patent number: 7989867
    Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: August 2, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mizuki Ono
  • Patent number: 7964970
    Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 21, 2011
    Assignee: Globalfoundries, Inc.
    Inventors: Martin Gerhardt, Ralf Richter, Thomas Feudel, Uwe Griebenow
  • Patent number: 7960780
    Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 7936021
    Abstract: In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Hoon Jeon, Satoru Yamada, Sang-Yeon Han, Jong-Man Park, Si-Ok Sohn
  • Patent number: 7919378
    Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: April 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Choong-Ho Lee, Dong-Gun Park, Chul Lee
  • Patent number: 7898057
    Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: March 1, 2011
    Assignee: HVVi Semiconductors, Inc.
    Inventors: Robert Bruce Davies, Warren Leroy Seely, Jeanne S Pavio
  • Patent number: 7868960
    Abstract: An active matrix substrate includes a plurality of transistors. A source electrode is connected with a data signal line, and a drain electrode is connected with a pixel electrode in each transistor. The source electrode is located on a semiconductor layer, and at least a portion of the drain electrode is overlapped with the gate electrode. A gate insulating film covering the gate electrode of each transistor has a thin section having a reduced film thickness, at a portion where the gate insulating film is overlapped with each gate electrode. An overlapping area of the thin section with the source electrode is smaller than an overlapping area of the thin section with the drain electrode. Thus, the active matrix substrate can prevent the generation of short-circuits between the signal lines (between the data signal line and a scanning signal line) in a TFT forming region, while guaranteeing TFT characteristics.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: January 11, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihide Tsubata, Yoshihiro Okada
  • Patent number: 7842951
    Abstract: A transistor includes a control electrode, a first current electrode and a second current electrode. The control electrode includes a body portion, and first and second hand portions protruded from first and second ends of the body portion, respectively. The first current electrode is electrically insulated from the control electrode and disposed over a region between the first and second hand portions of the control electrode. A portion of the first current electrode is overlapped with a portion of the control electrode. The second current electrode is electrically insulated from the control electrode and partially overlapped with the body portion, the first hand portion and the second hand portion of the control electrode. Therefore, parasitic capacitance is reduced.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: November 30, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Haeng-Won Park, Seung-Hwan Moon, Nam-Soo Kang, Yong-Soon Lee, Back-Won Lee
  • Patent number: 7808102
    Abstract: A DC-DC boost converter in multi-die package is proposed having an output Schottky diode and a low-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a single die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the single die pad via an insulating die bond. Alternatively, the single die pad is grounded. The vertical MOSFET is a top drain vertical N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the single die pad. The PRC is attached atop the single die pad via a standard conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: October 5, 2010
    Assignee: Alpha & Omega Semiconductor, Ltd.
    Inventors: François Hébert, Ming Sun
  • Patent number: 7795641
    Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; characterised in that the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: September 14, 2010
    Assignee: RFMD (UK) Limited
    Inventor: John Stephen Atherton
  • Patent number: 7786529
    Abstract: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: August 31, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Sik Kim
  • Patent number: 7714380
    Abstract: A semiconductor device includes a pair of first source/drain regions disposed on a silicon substrate. A first silicon epitaxial layer pattern defines a gate forming region that exposes the silicon substrate between the pair of first source/drain regions. A first gate insulation layer is disposed on the silicon substrate in the gate forming region. A second gate insulation layer is disposed on a sidewall of the first silicon epitaxial layer pattern. A second silicon epitaxial layer pattern is disposed in the gate forming region and on the first silicon epitaxial layer pattern. A pair of second source/drain regions is disposed on the second silicon epitaxial layer pattern. A third gate insulation layer exposes the second silicon epitaxial layer pattern in the gate forming region and covers the pair of second source/drain regions. A gate is disposed on the second silicon epitaxial layer pattern in the gate forming region.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: May 11, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Tae-Hong Lim
  • Publication number: 20100109099
    Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 6, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Atsuhiro Kinoshita
  • Patent number: 7692222
    Abstract: A semiconductor structure and method wherein a recess is disposed in a surface portion of a semiconductor structure and a dielectric film is disposed on and in contract with the semiconductor. The dielectric film has an aperture therein. Portions of the dielectric film are disposed adjacent to the aperture and overhang underlying portions of the recess. An electric contact has first portions thereof disposed on said adjacent portions of the dielectric film, second portions disposed on said underlying portions of the recess, with portions of the dielectric film being disposed between said first portion of the electric contact and the second portions of the electric contact, and third portions of the electric contact being disposed on and in contact with a bottom portion of the recess in the semiconductor structure. The electric contact is formed by atomic layer deposition of an electrically conductive material over the dielectric film and through the aperture in such dielectric film.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: April 6, 2010
    Assignee: Raytheon Company
    Inventors: Kamal Tabatabaie, Robert B. Hallock
  • Patent number: 7691752
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Pushkar Ranade, Keith Zawadzki, Christopher Auth
  • Patent number: 7663237
    Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Ching Peng, Chloe Hsin-yi Chen, David Hsu-Wei Lwu, Shyue-Shyh Lin, Wei-Ming Chen
  • Patent number: 7642141
    Abstract: A manufacturing method for a display device having a first conductive type thin film transistor and a second conductive type thin film transistor, comprising the steps of: in formation regions for a first conductive type thin film transistor and a second conductive type thin film transistor forming a semiconductor layer, a first insulating film covering the semiconductor layer and a gate electrode disposed on the first insulating film so as to intersect the semiconductor layer, on substrate having first conductive type impurity regions on both outer sides of a channel region of the semiconductor layer below the gate electrode forming a second insulating film, in the second insulating film and the first insulating film forming a contact hole for a drain electrode and a source electrode, in the formation region for the second conductive type thin film transistor forming electrodes and a second conductive type impurity region.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 5, 2010
    Assignee: Hitachi Displays, Ltd.
    Inventors: Yoshiaki Toyota, Takeshi Sato
  • Patent number: 7598146
    Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 6, 2009
    Assignee: STMicroelectronics, Inc.
    Inventor: Robert Louis Hodges
  • Patent number: 7569896
    Abstract: A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: August 4, 2009
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Chung-Hu Ke, Hung-Wei Chen, Wen-Chin Lee
  • Patent number: 7528439
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: May 5, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Robert J. Burke, Anand Srinivasan
  • Patent number: 7521766
    Abstract: According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Choong-Ho Lee, Dong-Gun Park, Chul Lee
  • Patent number: 7492017
    Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Tahir Ghani
  • Publication number: 20080277735
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.
    Type: Application
    Filed: May 7, 2007
    Publication date: November 13, 2008
    Inventors: Chih-Hsin Ko, Hung-Wei Chen, Chung-Hu Ke, Ta-Ming Kuan, Wen-Chin Lee
  • Patent number: 7397126
    Abstract: The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is formed so as to surround a periphery of the source electrode 4.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: July 8, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Tomoki Kato
  • Patent number: 7352031
    Abstract: A compact electrostatic-breakdown-preventive and protective circuit for a semiconductor-device capable of performing high-speed operations includes first and second protective transistors. The distance from a contact hole for connecting an impurity diffusion layer serving as a source and a drain of each of the first and second protective transistors with a metallic wiring, to gates of the protective transistors, is made shorter than a corresponding distance in an output transistor or a protective transistor provided for an input terminal.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: April 1, 2008
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Katsuhiro Kato
  • Patent number: 7332754
    Abstract: In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: February 19, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Uno, Manabu Yanagihara, Hidetoshi Ishida, Tsuyoshi Tanaka