Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, first and second cells electrically connected to the first load terminal structure and to a drift region, the drift region having a first conductivity type; a first mesa in the first cell and including: a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region; a second mesa in the second cell and including: a port region of the opposite conductivity type and electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure. The insulation structure houses a control electrode structure, and a guidance electrode arranged between the mesas.

Abstract: A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Abstract: A thin film transistor, its manufacturing method, and a display device are provided. The method comprises: forming a gate metal layer (35), forming a step-like gate structure (352) by one patterning process; performing a first ion implantation procedure to forming a first heavily doped area (39a) and a second heavily doped area (39b), the first heavily doped area (39a) being separated apart from the second heavily doped area (39b) by a first length; forming a gate electrode (353) from the step-like gate structure (352); performing a second ion implantation procedure to form a first lightly doped area (38a) and a second lightly doped area (38b), the first lightly doped area (38a) being separated apart from the second lightly doped area (38b) by a second length less than the first length. By the above method, the process for manufacturing the LTPS TFT having the lightly doped source/drain structure can be simplified.

Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other.

Abstract: A transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer.

Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed.

Abstract: A semiconductor device includes a gate electrode formed over a semiconductor substrate, and a sidewall spacer formed on a sidewall of the gate electrode. The sidewall spacer formed along the sidewall parallel to a gate length direction of the gate electrode has a first thickness, and the sidewall spacer formed along the sidewall parallel to a gate width direction of the gate electrode has a second thickness that is greater than the first thickness.

Abstract: In a method of manufacturing a semiconductor device, a buried layer is formed in a region of a semiconductor substrate and an epitaxial growth layer is formed on the buried layer and the semiconductor substrate. Trenches are formed in the epitaxial growth layer so as to be arranged side by side in a gate width direction of a transistor to be formed, and so that an entire bottom surface of each trench is entirely surrounded by and disposed in contact with the buried layer. A gate electrode is formed inside and on a top surface of each of the trenches and on a surface of the epitaxial growth layer adjacent to each of the trenches via a gate insulating film. A high concentration source diffusion layer is formed on one side of the gate electrode. A high concentration drain diffusion layer is formed on another side of the gate electrode.

Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having at least a dummy gate, a sacrificial layer covering sidewalls of the dummy gate and a dielectric layer exposing a top of the dummy gate formed thereon, forming a sacrificial layer covering sidewalls of the dummy gate on the substrate, forming a dielectric layer exposing a top of the dummy gate on the substrate, performing a first etching process to remove a portion of the sacrificial layer surrounding the top of the dummy gate to form at least a first recess, and performing a second etching process to remove the dummy gate to form a second recess. The first recess and the second recess construct a T-shaped gate trench.

Abstract: A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

Abstract: A transistor is provided that includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

Abstract: A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semiconductor layer adjacent to the first sidewall of the select gate. The thin layer of charge storage material is formed in which a first portion of the thin layer of charge storage material is formed in the first recess and a second portion of the thin layer of charge storage material is formed along the first sidewall of the first select gate. The control gate is formed over the first portion of the thin layer of charge storage material. The result is a semiconductor device useful a memory cell.

Abstract: There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer, a trench formed by digging the semiconductor layer from the surface thereof, a gate insulating film formed on the inner surface of the trench, and a gate electrode made of silicon embedded in the trench through the gate insulating film. The gate electrode has a high-conductivity portion formed to cover the gate insulating film with a relatively high conductivity and a low-conductivity portion formed on a region inside the high-conductivity portion with a relatively low conductivity.

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed.

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: Disclosed herein is a semiconductor device including a semiconductor substrate provided with an N-type FET and P-type FET, with a gate electrode of the N-type FET and a gate electrode of the P-type FET having undergone full-silicidation, wherein the gate electrode of the P-type FET has such a sectional shape in the gate length direction that the gate length decreases as one goes upwards from a surface of the semiconductor substrate, and the gate electrode of the N-type FET has such a sectional shape in the gate length direction that the gate length increases as one goes upwards from the surface of the semiconductor substrate.

Abstract: A gate structure includes a gate insulation layer pattern, a gate electrode, a first spacer and a protecting layer pattern. The gate insulation layer pattern is on a substrate. The gate electrode is on the gate insulation layer pattern, the gate electrode including a lower portion having a first width, a central portion having a second width smaller than the first width and an upper portion having a third width. The first spacer is on a lower sidewall of the gate electrode. The protecting layer pattern is on a central sidewall of the gate electrode.

Abstract: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Abstract: A silicon nitride film, which is a second hard mask, is dry etched to be removed completely. The silicon nitride film, which is formed on a sidewall of a silicon nitride film used as a first hard mask, has a relatively low etching rate. Therefore, if the silicon nitride film is continued etching until the corresponding portion thereof is removed, polysilicon is etched in a direction of depth in trench shape. Then, floating gates in adjacent cells are separated and a step portion of the polysilicon is formed. Consequently, a remaining portion of the silicon nitride film used as the first hard mask is removed, an ONO film is laminated on a whole surface of the poly silicon having the step portion on an edge that has been etched, and then, a polysilicon for a control gate is laminated on the ONO film.

Abstract: A semiconductor device and a method of fabricating the same include a gate electrode formed over the silicon substrate, the gate electrode including low-concentration conductive impurity regions, a high-concentration conductive impurity region formed between the low-concentration conductive impurity regions and a first silicide layer formed over the high-concentration conductive impurity region, and contact electrodes including a first contact electrode connected electrically to the gate electrode and a second contact electrode connected electrically to source/drain regions. The first contact electrode contacts the uppermost surface of the gate electrode and a sidewall of the gate electrode. The gate electrode can be easily connected to the contact electrode, the high-concentration region can be disposed only on the channel region, making it possible to maximize overall performance of the semiconductor device.

Abstract: A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall.

Abstract: A semiconductor device includes a semiconductor substrate, a first and second semiconductor regions formed on the semiconductor substrate insulated and separated from each other, a gate dielectric film formed on the substrate to overlap the first and second semiconductor regions, a floating gate electrode formed on the gate dielectric film and in which a coupling capacitance of the first semiconductor region is larger than that of the second semiconductor region, first source and drain layers formed on the first semiconductor region to interpose the floating gate electrode therebetween, a first and second wiring lines connected to the first source and drain layers, respectively, second source and drain layers formed on the second semiconductor region to interpose the floating gate electrode therebetween, and a third wiring line connected to the second source and drain layers in common.

Abstract: A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion.

Abstract: In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

Abstract: A semiconductor structure includes a first finFET and a second finFET. The first finFET and the second finFET may comprise an n-finFET and a p-finFET to provide a CMOS finFET structure. Within the semiconductor structure, at least one of: (1) a first gate dielectric within the first finFET and a second gate dielectric within the second finFET comprise different gate dielectric materials; and/or (2) a first gate electrode within the first finFET and a second gate electrode within the second finFET comprise different gate electrode materials.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: The semiconductor device includes an active region, a stepped recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The stepped recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the stepped recess channel region. The gate structure is disposed over the stepped recess channel region of the gate region.

Abstract: A method for creating a non-volatile memory array includes implanting pocket implants in a substrate at least between mask columns of a given width and at least through an ONO layer covering the substrate, generating increased-width polysilicon columns from the mask columns, generating bit lines in the substrate at least between the increased-width polysilicon columns and depositing oxide at least between the polysilicon columns.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.

Abstract: A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion.

Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.

Abstract: Provided is a switch device that can be reliably turned on or off using a nanostructure that includes a nanotube and/or a nanowire. The switch device includes a lower conductive film formed on a substrate, a first insulating film formed on the lower conductive film and having a first hole that exposes at least a portion of the first lower conductive film, and a conductive film spacer formed on an inner wall of the first hole of the first insulating film. A switch device may include a nanostructure having an end electrically connected to the lower conductive film, including a nanotube and/or a nanowire, extending substantially vertically from the lower conductive film and penetrating through the first hole, and separated from the conductive film spacer with a working gap interposed therebetween.

Abstract: A semiconductor device includes: an isolation region formed in a semiconductor substrate; a first active region and a second active region surrounded by the isolation region; an n-type gate electrode and a p-type gate electrode formed on gate insulating films; an insulating film and a silicon region formed on the isolation region and isolating the n-type gate electrode and the p-type gate electrode from each other; and a metal silicide film formed on the upper surfaces of the n-type gate electrode, the silicon region, the p-type gate electrode, and part of the insulating film formed therebetween. The n-type gate electrode is electrically connected to the p-type gate electrode through the metal silicide film.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.