Abstract: A semiconductor device of embodiments includes a first gate electrode, a second gate electrode, a third gate electrode extending in a first direction, and a gate wiring line extending in a second direction crossing the first direction and to which the first to the third gate electrodes are connected. Assuming distance between the first and the second gate electrode in the second direction in a first region is S1, distance between the first and the second gate electrode in the second direction in a second region closer to the gate wiring line than the first region is S2, distance between the second and the third gate electrode in the second direction in the first region is S3, and distance between the second and the third gate electrode in the second direction in the second region is S4, following Expressions are satisfied, S1<S3, S1<S2, S3>S4.

Abstract: An integrated circuit includes at least one decoupling cell, wherein the at least one decoupling cell includes at least one P-type decoupling MOSFET and at least one N-type decoupling MOSFET, and a number of the at least one P-type decoupling MOSFET is different from a number of the at least one N-type decoupling MOSFET.

Abstract: A semiconductor structure includes a substrate, an isolation layer, a dielectric layer, an insulation layer, a conductor and a capping layer. The substrate has a concave portion. The isolation layer is located on a top surface of the substrate. The dielectric layer is located on the isolation layer. The insulation layer is located on a surface of the concave portion and extends to a sidewall of the isolation layer. The conductor is located on the insulation layer in the concave portion. The conductor has a first top surface and a second top surface, and the first top surface is closer to the dielectric layer than the second top surface. The capping layer is located in the concave portion and covers the conductor.

Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.

Abstract: A method for making a super junction device includes the following steps: step 1: forming a trench gate, in the forming process of the trench gate, a polysilicon gate being used to fill gate trenches and then first flattening being performed and the width of the gate trench at the leading-out position of the gate structure satisfies the requirement of forming contacts; and step 2: forming a super junction, in the forming process of the super junction, a second epitaxial layer being used to fill a super junction trench and then second flattening being performed. The method can realize an all flat process, can conveniently arrange the trench gate process before the forming process of the super junction, can decrease the thermal processes after the formation of the super junction, can save the mask and can decrease the process cost.

Abstract: Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0?x?1, 0?y?1, 0?x+y?1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm?1 or more and 4.6 cm?1 or less under a temperature condition of normal temperature.

Abstract: Described at light emitting diode (LED) devices emitting different colors on the same wafer, which facilitates their integration with close packing density (not requiring transfer of devices from two different wafers to a third substrate module). The LED devices and driving methods allow light of different colors and similar luminance levels to be emitted for given input current.

Abstract: A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: A wide gap semiconductor device has: a drift layer using wide gap semiconductor material being a first conductivity type; a well region being a second conductivity type and provided in the drift layer; a source region provided in the well region; a gate contact region provided in the well region and electrically connected to a gate pad; and a Zener diode region provided in the well region and provided between the source region and the gate contact region.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Abstract: An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.

Abstract: A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars.

Abstract: A method including forming a dummy gate on a substrate, wherein the dummy gate includes an oxide, forming a pair of dielectric spacers on opposite sides of the dummy gate, and forming an inter-gate region above the substrate and in contact with at least one of the pair of dielectric spacers, the inter-gate region comprising a protective layer on top of a first oxide layer, wherein the protective layer comprises a material resistant to etching techniques designed to remove oxide. The method may further include removing the dummy gate to leave an opening, and forming a gate within the opening.

Abstract: A semiconductor device includes a trench extending from a surface of a P-base layer to a surface of a P-well layer. The trench has a trench end portion defined in the surface of the P-well layer and in a direction in which the trench extends. The trench has first and second regions. The first region extends from the trench end portion to get into the surface of the P-base layer near a boundary between the P-base layer and the P-well layer. The second region extends in the surface of the P-base layer from an end portion of the first region. A trench width is greater in the first region than in the second region.

Abstract: An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers.

Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: A system and method for manufacturing multiple-gate semiconductor devices is disclosed. An embodiment comprises multiple fins, wherein intra-fin isolation regions extend into the substrate less than inter-fin isolation regions. Regions of the multiple fins not covered by the gate stack are removed and source/drain regions are formed from the substrate so as to avoid the formation of voids between the fins in the source/drain region.

Abstract: A semiconductor device includes source fingers and drain fingers provided on an active region of a nitride semiconductor layer alternately, gate fingers having a side edge and a distal edge, a first insulation film provided on the nitride semiconductor layer and covers a top face, the side and distal edges of the gate fingers, field plates provided on the first insulation film between the gate fingers and the drain fingers, a minimum distance between the side face of the first insulation film located on the side edge of the gate fingers and the field plate being at least 100 nm, and field plate interconnections provided on the first insulation film and located outside of the active region and electrically connected with the source fingers and the field plates, a minimum distance between the side face of the first insulation film located on the distal edge of the gate fingers and the field plate interconnections being at least 100 nm.

Abstract: Provided is a thin film device and an associated method of making a thin film device. For example, a thin film transistor with nano-gaps in the gate electrode. The method involves providing a substrate. Upon the substrate are then provided a plurality of parallel spaced electrically conductive strips. A plurality of thin film device layers are then deposited upon the conductive strips. A 3D structure is provided upon the plurality of thin film device layers, the structure having a plurality of different heights. The 3D structure and the plurality of thin film device layers are then etched to define a thin film device, such as for example a thin film transistor that is disposed above at least a portion of the conductive strips.

Abstract: A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.

Abstract: A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.

Abstract: A semiconductor device is provided that uses a floating gate to store analog- and digital-valued information for periods of time measured in milliseconds to hours. Charge is added to and/or removed from the floating gate by means of direct electron tunneling through the surrounding insulator, with the insulator typically being thin enough such that appreciable tunneling occurs with an insulator voltage smaller than the difference in electron affinities between the semiconductor and the insulator and/or between the floating gate and the insulator. The stored information is refreshed or updated as needed. In many applications, the stored information can be refreshed without interrupting normal circuit operation. Adding and removing charge to or from the floating gate may be performed using separate circuit inputs, to tailor the performance and response of the floating-gate device. There is no need to use a control gate in the floating-gate structures disclosed herein.

Abstract: Disclosed is a semiconductor storage device having a trench around a bit-line diffusion region in an area of a p-well, which constitutes a memory cell area, that is not covered by a word line and a select gate that intersects the word line. An insulating film is buried in the trench.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: A semiconductor device has a first and a second active regions of a first conductivity type disposed on a semiconductor substrate, a third and a fourth active regions of a second conductivity type disposed on the semiconductor substrate, the second and the fourth active regions having sizes larger than those of the first and the third active regions respectively, a first electroconductive pattern disposed adjacent to the first active region and having a first width, a second electroconductive pattern disposed adjacent to the second active region and having a second width larger than the first width, a third electroconductive pattern disposed adjacent to the third active region and having a third width; and a fourth electroconductive pattern disposed adjacent to the fourth active region and having a fourth width smaller than the third width.

Abstract: A trench MOSFET with copper metal connections includes a substrate provided with a plurality of trenches. A gate oxide layer is formed on the sidewalls and bottoms of the trenches. A conductive layer is filled in the trenches to be used as a gate of the MOSFET. A plurality of source and body regions are formed in an epi layer. An insulating layer is formed on the epi layer and formed with a plurality of metal contact holes therein for contacting respective source and body regions. A barrier metal layer is formed on the sidewalls and bottoms of the metal contact holes in direct contact with respective source and body regions. A metal contact layer is filled in the metal contact holes. A copper metal layer is formed on another barrier metal layer on the insulating layer connected to respective source regions through the metal contact layer to form metal connections of the MOSFET.

Abstract: On a major surface of an n-type silicon carbide inclined substrate (2) is formed an n-type voltage-blocking layer (3) made of silicon carbide by means of epitaxial growth. On the n-type voltage-blocking layer (3) is formed a p-type silicon carbide region (4) rectangular when viewed from above. On the surface of the p-type silicon carbide region (4) is formed a p-type contact electrode (5). In the p-type silicon carbide region (4), the periphery of the p-type silicon carbide region (4) that is parallel with a (11-20) plane (14a) of the silicon carbide crystal, which is liable to cause avalanche breakdown, is located on the short side. In this manner, the dielectric strength of a silicon carbide semiconductor device can be improved.

Abstract: A semiconductor device includes an active region extending along a first direction on a semiconductor substrate, the active region having a first sidewall and a second sidewall spaced apart and facing each other, a distance between the first and second sidewalls extending along a second direction, and a gate on the active region, the gate having a pair of body portions extending along the second direction and being spaced apart from each other, the second direction being perpendicular to the first direction, a head portion extending along the first direction to connect the body portions, the head portion overlapping a portion of the first sidewall, and a plurality of tab portions protruding from sidewalls of the body portions, the tab portions extending along the first direction and overlapping a portion of the second sidewall.

Abstract: There are provided a TFT, a TFT substrate using the TFT, a method of fabricating the TFT substrate, and an LCD. The TFT includes a source region, a drain region, and a gate electrode having an opening. The opening of the gate electrode is to enhance the light sensing ability of the TFT when it is used as a light sensor, since light is incident into a region where the opening is formed. The TFT including the gate having the opening can be used in a substrate of a flat display or an LCD using such a substrate. The above TFT can sense light incident from outside the display to adjust the brightness of the screen according to the external illumination.

Abstract: A photo mask and a semiconductor device fabricated using the same is disclosed. The photo mask to form a mask pattern defining a STAR gate region includes a transparent substrate, and a light-shielding pattern defining a zigzag W-STAR gate region, wherein a waved portion of the light-shielding pattern partially overlaps a gate region and a storage node contact region of an active region disposed on a semiconductor substrate. The semiconductor device includes an active region and a device isolation region defining the active region disposed in a semiconductor substrate, a gate electrode, wherein a line width of the gate electrode in the active region is greater than that in the device isolation region, and a zigzag W-STAR gate region, wherein the waved portion of the zigzag W-STAR gate region partially overlaps the gate region and the storage node contact region in the active region.

Abstract: A semiconductor device for determining an overlay error on a semiconductor substrate includes a first and a second transistor. Each transistor includes two diffusion regions associated with a gate, the diffusion regions of each transistor being arranged in a first direction. The second transistor is arranged adjacent to the first transistor in a second direction perpendicular to the first direction. The first and second gate each have a non-uniform shape, and the second gate is oriented with respect to an orientation of the first gate in such a way that an effect of an overlay error on a device parameter of the second transistor has an opposite sign in comparison to an effect of the overlay error on a corresponding device parameter of the first transistor.

Abstract: A semiconductor device comprises a drift region of a first conduction type, a base region of a second conduction type, a source region of the first conduction type, a contact hole, a column region of the second conduction type, a plug and wiring. The drift region formed on a semiconductor substrate of the first conduction type. The base region of a second is formed in a prescribed region of the surface of the drift region. The source region is formed in a prescribed region of the surface of the base region. The contact hole extends from the source region surface side to the base region. The column region is formed in the drift region below the contact hole. The plug comprises a first conductive material and fills the contact hole. The wiring comprises a second conductive material and is electrically connected to the plug.

Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.

Abstract: A power semiconductor device includes a semiconductor substrate having a plurality of trenches formed in an upper surface thereof; a buried insulating film; a buried field plate electrode; a control electrode; a first main electrode provided on a lower side of the semiconductor substrate; and a second main electrode provided on an upper side of the semiconductor substrate. The semiconductor substrate includes: a first semiconductor; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type; a fourth semiconductor layer; and a fifth semiconductor layer. The buried insulating film is thicker than a gate insulating film. At least one of the second semiconductor layer and the third semiconductor layer has a portion with its sheet dopant concentration varying along a depth direction of the semiconductor substrate.

Abstract: A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26, 28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential plates (60) that act together with source and drain drift regions (30, 32) to create a RESURF effect.

Abstract: The specification describes an improved mechanical electrode structure for MOS transistor devices with elongated runners. It recognizes that shrinking the geometry increases the likelihood of mechanical failure of comb electrode geometries. The mechanical integrity of a comb electrode is improved by interconnecting the electrode fingers in a cross-connected grid. In one embodiment, the transistor device is interconnected with gate fingers on a lower metaliization level, typically the first level metal, with the drain interconnected at a higher metal level. That allows the drain fingers to be cross-connected with a vertical separation between drain and gate comb electrodes. The cross-connect members may be further stabilized by adding beam extensions to the cross-connect members. The beam extensions may be anchored in an interlevel dielectric layer for additional support.

Abstract: Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

Abstract: Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.