Abstract: A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate, a light-emitting element layer provided on the thin-film transistor layer; and a sealing film provided on the light-emitting element. Each of light-emitting elements includes: a first electrode; a functional layer; and a second electrode stacked on top of another in a stated order. The display device includes: a display region; a frame region; and a non-display region. The non-display region includes a through hole. The display device includes a separation wall shaped into a frame and provided to the non-display region along an edge of the through hole. The separation wall includes: a first resin layer: and a first metal layer provided on the first resin layer. The first metal layer includes a first protrusion shaped into a canopy, and protruding from the first resin layer toward the display region.

Abstract: Second Harmonic Generation (SHG) can be used to interrogate a surface such as a surface of a layered semiconductor structure on a semiconductor wafer. In some instances, SHG is used to evaluate an interfacial region such as between metal and oxide. Various parameters such as input polarization, output polarization, and azimuthal angle of incident beam, may affect the SHG signal. Accordingly, such parameters are varied for different types of patterns on the wafer. SHG metrology on various test structures may also assist in characterizing a sample.

Abstract: To reduce power consumption of a display device with the use of a simple structure and a simple operation. The display device includes an input device. Input of an image signal to a driver circuit is controlled in accordance with an image operation signal output from the input device. Specifically, input of image signals at the time when the input device is not operated is less frequent than that at the time when the input device is operated. Accordingly, display degradation (deterioration of display quality) caused when the display device is used can be prevented and power consumed when the display device is not used can be reduced.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: An electronic device is provided. The electronic device includes a substrate, a driving circuit, a diode and a light shielding element. The driving circuit is disposed on the substrate. The diode is electrically connected to the driving circuit. The light shielding element overlaps the substrate. A surface of the light shielding element has a first width. A cross-sectional-surface of a portion of the light shielding element has a second width. In addition, the second width is greater than the first width in a cross-sectional view, and the surface is closer to the substrate than the cross-sectional surface of the portion.

Abstract: A display substrate and a manufacturing method thereof are provided. The display substrate has a first side and a second side opposite to the first side, and the display substrate includes a display region, the display region includes a first display region and a second display region at least partially surrounding the first display region, the first display region allows light from the first side to be at least partially transmitted to the second side; and the display substrate further includes at least one first connection wire in both of the first display region and the second display region, the first connection wire includes a first portion in the first display region and a second portion in the second display region, the first portion and the second portion are electrically connected, the first portion includes a first light-transmitting wiring layer, and the second portion includes a metal wiring layer.

Abstract: An array substrate includes a substrate, a first metal layer and an active layer disposed on the substrate, an interlayer insulating layer, and a second metal layer. The first metal layer forms at least one first trace, the interlayer insulating layer is disposed on the first metal layer and the active layer, the second metal layer is disposed on the interlayer insulating layer, the interlayer insulating layer is formed with a first contact hole, and the second metal layer is connected to the first trace through the first contact hole. The first metal layer includes a conductive layer and a first protective layer stacked in sequence.

Abstract: A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer.

Abstract: A method of manufacturing an organic light-emitting display device is provided. The method includes: forming a lower electrode pattern on a substrate, which includes a transistor area and a capacitor area, to correspond to the transistor area and forming a buffer layer on the substrate including the lower electrode pattern; forming a thin-film transistor including an oxide semiconductor layer on the buffer layer; forming an interlayer insulating film on the thin-film transistor; forming a photoresist film pattern including first and second holes, which have different depths, on the interlayer insulating film; and forming a first contact hole, which exposes the lower electrode pattern, and second contact holes, which expose the oxide semiconductor layer, at the same time using the photoresist film pattern.

Abstract: A semiconductor device includes a semiconductor layer over a substrate; a gate insulating film covering the semiconductor layer; a gate wiring including a gate electrode, which is provided over the gate insulating film and is formed by stacking a first conductive layer and a second conductive layer; an insulating film covering the semiconductor layer and the gate wiring including the gate electrode; and a source wiring including a source electrode, which is provided over the insulating film, is electrically connected to the semiconductor layer, and is formed by stacking a third conductive layer and a fourth conductive layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. The source electrode is formed using the third conductive layer. The source wiring is formed using the third conductive layer and the fourth conductive layer.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.

Abstract: A manufacturing method of display panel, a display panel and a display device are disclosed. The manufacturing method includes following steps: providing a substrate, forming a first barrier layer on the substrate, forming a conductive layer on the first barrier layer, forming a second barrier layer on the conductive layer, forming a photoresist pattern on the second barrier layer, and then performing a plasma treatment on the photoresist pattern to form a first gap between the photoresist pattern and the second barrier layer.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.

Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.

Abstract: Methods for selective silicon film deposition on a substrate comprising a first surface and a second surface are described. More specifically, the process of depositing a film, treating the film to change some film property and selectively etching the film from various surfaces of the substrate are described. The deposition, treatment and etching can be repeated to selectively deposit a film on one of the two substrate surfaces.

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: A display device includes a data conductive layer disposed on a substrate, a passivation layer disposed on the data conductive layer, a via layer disposed on the passivation layer, and a pixel electrode disposed on the via layer. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a third data capping layer disposed on the second data capping layer. The passivation layer and the via layer include a pad opening which exposes a portion of the data conductive layer in the pad area. The third data capping layer has a higher etch rate than the first and second data capping layers for a same etchant.

Abstract: A method for activating a cell-signaling pathway of interest in a cell, including applying a time-modulated localized alternating current electrical field to the cell, wherein the amplitude and frequency of the localized alternating current electrical field is selected to activate the cell signaling pathway of interest, thereby activating the cell signaling pathway.

Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

Abstract: Disclosed are a display panel, a manufacturing method thereof, and a display device. The display panel includes a base substrate and sub-pixels thereon. At least one sub-pixel includes: a light emitting element including a first electrode, a luminous functional layer and a second electrode sequentially stacked, the first electrode being closer to the base substrate than the second electrode; a metal reflective layer, between the base substrate and the first electrode; a silicon nitride layer, between the first electrode and the metal reflective layer, and including a first via hole through which the first electrode is connected with the metal reflective layer; a driving circuit including a driving transistor and a storage capacitor between the base substrate and the metal reflective layer, the driving transistor including a gate electrode connected with the storage capacitor, and source and drain electrodes, one of which is connected with the metal reflective layer.

Abstract: A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor.

Abstract: A liquid crystal display device includes, in order from an observation surface side to a hack surface side, a thin film transistor substrate including a color filter layer, a pair of electrodes, and a metal wiring line, a liquid crystal layer containing liquid crystal molecules that are horizontally aligned to the thin film transistor substrate and in which alignment of the liquid crystal molecules is changed due to an electric field generated by applying a voltage to the pair of electrodes, a counter substrate, and a backlight, in which the counter substrate includes a reflective layer disposed outside the pixel area and reflecting incident light from the backlight to the back surface side, the pair of electrodes are a first electrode having a planar shape and a second electrode provided with a and the color filter layer is disposed on the observation surface side of the second electrode.

Abstract: Disclosed are a display panel, a manufacturing method thereof, and a display device. The display panel includes a base substrate and sub-pixels thereon. At least one sub-pixel includes: a light emitting element including a first electrode, a luminous functional layer and a second electrode sequentially stacked, the first electrode being closer to the base substrate than the second electrode; a metal reflective layer, between the base substrate and the first electrode; a silicon nitride layer, between the first electrode and the metal reflective layer, and including a first via hole through which the first electrode is connected with the metal reflective layer; a driving circuit including a driving transistor and a storage capacitor between the base substrate and the metal reflective layer, the driving transistor including a gate electrode connected with the storage capacitor, and source and drain electrodes, one of which is connected with the metal reflective layer.

Abstract: A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.

Abstract: A method of manufacturing a photo sensor includes forming a first conductive layer on a substrate, the first conductive layer including a metal layer and a transparent conductive oxide layer formed on the metal layer, forming a photoconductive layer on the first conductive layer, forming a second conductive layer on the photoconductive layer, forming a first photoresist pattern on the second conductive layer, etching the second conductive layer using the first photoresist pattern as an etch mask to form a second electrode, deforming the first photoresist pattern to form a second photoresist pattern, and etching the photoconductive layer and the first conductive layer using the second photoresist pattern to form a photoconductive pattern and a first electrode, respectively.

Abstract: A display panel includes a base, at least one separation pillar, at least one protection pattern, and a light-emitting functional layer. The at least one separation pillar is disposed in the isolation region on the base, each separation pillar is disposed around the opening region, and a longitudinal section of the separation pillar perpendicular to an extending direction of the separation pillar is I-shaped. The at least one protection pattern is disposed on a surface of at least one separation pillar facing away from the base. The light-emitting functional layer is disposed at least in both the pixel region and the isolation region on a surface of the at least one protection pattern facing away from the base, wherein the light-emitting functional layer is disconnected at an inner side face and an outer side face of the separation pillar.

Abstract: A display device includes a base layer, a display element disposed on the base layer, and a signal line disposed on the base layer and electrically connected to the display element. The signal line includes a conductive layer and a capping layer. The capping layer is disposed on the conductive layer and includes vanadium nitride (VN) and zinc oxide (ZnO). The display device may reduce the reflection of an external light source, thereby having improved visibility.

Abstract: According to one embodiment, an electronic apparatus includes a first substrate, a second substrate, and a connecting material. The second substrate includes a second basement and a second conductive layer. The second basement has a third surface opposed to the first conductive layer and a fourth surface and is spaced apart from the first conductive layer. The second substrate has a first hole penetrating the second basement. The first substrate has a second hole. A third opening of the second hole is smaller than a first opening of the first hole. A connecting material connects the first conductive layer and the second conductive layer via the first hole.

Abstract: An array substrate, a manufacture method thereof, and a display device are provided. The array substrate includes a first electrode (12), a second electrode (15); a light-emitting functional layer (13) located between the first electrode (12) and the second electrode (15); and an organic planar layer (14). The first electrode (12) is formed on the organic planar layer (14). The first electrode (12) includes metal electrode or metal alloy electrode. An oxide conductive layer (16) is further formed between the organic planar layer (14) and the first electrode (12).

Abstract: A liquid crystal display device includes: a lower substrate including a display unit and a non-display unit; an upper substrate opposing the lower substrate; a gate line and a data line disposed in the display unit of the lower substrate; a light shielding layer defining a pixel region of the lower substrate; a pixel electrode disposed in the pixel region of the lower substrate; a pixel transistor disposed in the display unit of the lower substrate and connected to the gate line, the data line, and the pixel electrode; a driving transistor disposed in the non-display unit of the lower substrate; a first protection layer disposed on the pixel transistor and the driving transistor; a shielding layer disposed on the first protection layer, the shielding layer overlapping at least one of the pixel transistor and the driving transistor; and a second protection layer disposed on the shielding layer.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: A display device includes a laminated wiring formed of a low-resistance conductive film, and a low-reflection film mainly containing Al and functioning as an antireflective film which are sequentially arranged on a transparent substrate, a wiring terminal part provided at an end part of the laminated wiring and has the same laminated structure as that of the laminated wiring, and an insulating film for covering the laminated wiring and the wiring terminal part, in which the insulating film side serves as a display surface side, the wiring terminal part has a first opening part penetrating the insulating film and the low-reflection film and reaching the low-resistance conductive film, and an outer peripheral portion of the first opening part has a laminated structure of the low-resistance conductive film, the low-reflection film, and the insulating film, in at least one part.

Abstract: An array substrate for an electrophoresis type display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes; a first passivation layer on the plurality of data lines; a second passivation layer on the first passivation layer, wherein the second passivation layer includes a first hole over the data line, and/or a second hole over the gate line with at least the gate insulating layer therebetween; and a pixel electrode on the second passivation layer and connected to the drain electrode, wherein a portion of the pixel electrode covers the first hole, and another portion of the pixel electrode covers the second hole.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: A thin film transistor array panel includes a passivation layer formed on a plurality of end portions of a plurality of gate lines. A portion of the passivation layer has a porous structure formed between a connection portion of a flexible printed circuit substrate and a thin film transistor substrate such that when the flexible printed circuit substrate and the thin film transistor array panel are connected to each other, the passivation layer having a porous structure and which is formed at the connection portion therebetween connects the flexible printed circuit substrate with the thin film transistor array panel thereby minimizing an exposed area of the metal of the connection portion to improve a corrosion resistance thereof.

Abstract: Provided is a display device capable of suppressing generation of optical leakage current as well as increase in capacitance in a case where a plurality of thin film transistors (TFTs) including a gate electrode film on a light source side are formed in series. Relative areas of opposing regions between a semiconductor film and the gate electrode film with respect to channel regions are different in at least a part of the plurality of TFTs, to thereby provide a flat panel display having a structure for suppressing increase in capacitance while suppressing generation of optical leakage current.

Abstract: Provided are an organic TFT that reduces contact resistance between a source and drain electrode and an organic semiconductor layer and that can be easily manufactured, a flat panel display device having the organic TFT, and methods of manufacturing the organic TFT and the flat panel display device having the same. The organic TFT includes; a substrate; a gate electrode and a blocking layer formed on the substrate; a gate insulating film covering the gate electrode and the blocking layer; a source electrode and a drain electrode located on the gate insulating film; an auxiliary source electrode and an auxiliary drain electrode respectively located on the source electrode and the drain electrode; and an organic semiconductor layer contacting the auxiliary source electrode and the auxiliary drain electrode.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have cooper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: An impurity element imparting one conductivity type is included in a layer close to a gate insulating film of layers with high crystallinity, so that a channel formation region is formed not in a layer with low crystallinity which is formed at the beginning of film formation but in a layer with high crystallinity which is formed later in a microcrystalline semiconductor film. Further, the layer including an impurity element is used as a channel formation region. Furthermore, a layer which does not include an impurity element imparting one conductivity type or a layer which has an impurity element imparting one conductivity type at an extremely lower concentration than other layers, is provided between a pair of semiconductor films including an impurity element functioning as a source region and a drain region and the layer including an impurity element functioning as a channel formation region.

Abstract: A thin film transistor comprising a gate electrode, a gate insulating layer, an active layer, and source and drain electrodes is provided. The gate electrode overlaps with a channel region of the active layer, the gate insulating layer is provided between the gate electrode and the active layer, the source and drain electrodes overlap a source region and a drain region of the active layer, respectively, and a thin film of SiNx or SiOxNy through which electrons are allowed to tunnel is provided between the active layer and the source and drain electrodes.

Abstract: A method for manufacturing a liquid crystal display includes the following steps. First, source/drain and a bottom electrode are formed over a color filter substrate with a color filter layer. The next step forms source/drain junction regions over the source/drain. A channel region is also formed between the source/drain in this step. A gate dielectric layer and a gate are formed over the channel region and the source/drain junction regions in this step as well. Moreover, a plurality of stack layers and an upper electrode are formed over the bottom electrode in this step, too. Then, a pixel electrode is formed to electrically connect one of the source/drain and the bottom electrode. Then, a passivation layer pattern is formed to cover the source/drain, the gate, the upper electrode and the bottom electrode by backside exposure. Finally, a plurality of steps are performed to finish the liquid crystal display.

Abstract: A liquid crystal display panel and a fabricating method thereof comprising an image sensing capability, image scanning, and touch inputting. In the liquid crystal display device, a gate line and a data line are formed to intersect each other on a substrate to define a pixel area in which a pixel electrode is positioned. A first thin film transistor is positioned at an intersection area of the gate line and the data line. A sensor thin film transistor senses light having image information and supplied with a first driving voltage from the data line. A driving voltage supply line is positioned in parallel to the gate line to supply a second driving voltage to the sensor thin film transistor.

Abstract: A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

Abstract: An image display device capable of high-resolution and smooth moving image display, equipped with TFTs in an n-type (or p-type) semiconductor layer with a high on-off ratio and a low resistance. In polysilicon crystallization by laser annealing, an n-type (or p-type) semiconductor layer with a low resistance is produced by performing the following processes in order: implanting nitrogen (N) ions into an amorphous silicon precursor semiconductor film; laser crystallization; implanting n-type (or p-type) dopant ions; and annealing for dopant activation. When fabricating TFTs, this low-resistance semiconductor layer is used to form a source and a drain. Since C, N, and O impurities decrease the mobility of the TFTs, polysilicon is used in which the contaminants concentrations meet the following conditions: carbon concentration ?3×1019 cm?3, nitrogen concentration ?5×1017 cm?3, and oxygen concentration ?3×1019 cm?3.

Abstract: A display panel structure having a circuit element disposed thereon and method of manufacture are provided. The display panel includes a substrate and the circuit element disposed on the substrate. The circuit element has a first interface layer and a first conductive layer. Both the first interface layer and the first conductive layer have copper materials. The material which makes the first interface layer includes a reactant or a compound of the material which makes the first conductive layer. The method for manufacturing includes the following steps: forming a first interface layer on the substrate; forming a first conductive layer on the first interface layer; and etching the first conductive and interface layers to form a pattern. The existence of the first interface reduces the penetration of the first conductive layer on the substrate and improves the adhesive force between the first conductive layer and the substrate.

Abstract: A substrate for a display device, includes: an insulation substrate; an insulation film, which is formed on the insulation substrate and is primarily made of one of silicon oxide and oxidized metal; an inorganic film, which is formed to be in direct contact with the insulation film and has an insulator part that is formed by changing oxide semiconductor into insulator; and a wiring film, which is formed to be in direct contact with the insulator part.