For Tft (epo) Patents (Class 257/E29.151)
  • Patent number: 10068809
    Abstract: The invention provides a manufacturing method for TFT backplane, through forming an oxygen-containing a-Si layer on the buffer layer and an oxygen-free a-Si layer on the oxygen-containing a-Si layer so that when using a boron induced SPC to crystallize the a-Si thin film, the contact interface between the a-Si thin film and the buffer layer is the oxygen-containing a-Si layer; because the nucleation is not easy to occur in oxygen-containing a-Si layer during high temperature crystallization, the nucleation only occurs top-down in the boron doped layer on the upper surface of the a-Si thin film for good die quality and thin film uniformity to achieve improve crystalline quality and uniformity. The TFT backplane provided by the invention is made with simple process, wherein the crystalline quality and uniformity of the polysilicon layer is preferable, and can enhance the TFT performance and the driving effect.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: September 4, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xingyu Zhou
  • Patent number: 10026758
    Abstract: An array substrate, a manufacturing method thereof, a display panel and a display device are disclosed. The manufacturing method includes: forming a first metal wiring, an interlayer insulating film, a second metal wiring and a protecting layer in sequence on a substrate, the second metal wiring is parallel with the first metal wiring and has an overlapped area therewith which is defined as a first zone, and portions of the first and second metal wiring except the first zone are defined as a second zone and a third zone respectively; at least thinning a portion of the interlayer insulating film and/or the protecting layer corresponding to the first zone while leaving portions except those corresponding to the first, second and third zones un-thinned. The manufacturing method can mitigate Zara mura.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 17, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ruirui Wang, Huabin Chen, Linlin Wang, Xiaopeng Cui
  • Patent number: 10026754
    Abstract: The object of the present invention is to make it possible to form an LIPS TFT and an oxide semiconductor TFT on the same substrate. A display device includes a substrate having a display region in which pixels are formed. The pixel includes a first TFT using an oxide semiconductor 109. An oxide film 110 as an insulating material is formed on the oxide semiconductor 109. A gate electrode 111 is formed on the oxide film 110. A first electrode 115 is connected to a drain of the first TFT via a first through hole formed in the oxide film 110. A second electrode 116 is connected to a source of the first TFT via a second through hole formed in the oxide film 110.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 17, 2018
    Assignee: Japan Dispaly Inc.
    Inventors: Isao Suzumura, Kazufumi Watabe, Yoshinori Ishii, Hidekazu Miyake, Yohei Yamaguchi
  • Patent number: 9905592
    Abstract: A method for manufacturing a thin-film transistor (TFT), an array substrate and a display device are disclosed. The manufacturing method includes: forming a photoresist layer provided with a completely retained region, a partially-retained region and a completely removed region on a metal film by a half-tone mask process; forming a source/drain metal layer by etching the metal film under the cover of the photoresist layer; removing the photoresist layer in the partially-retained region; forming an active layer by patterning the semiconductor film; and removing residual photoresist layer.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: February 27, 2018
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tongshang Su, Shengping Du, Ning Liu, Dongfang Wang, Guangcai Yuan
  • Patent number: 9391207
    Abstract: The present invention provides a low-temperature polysilicon thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device. The present invention is related to display technology. The low-temperature polysilicon thin film transistor comprises: an active layer disposed on a substrate, and a source electrode and a drain electrode respectively connected to the active layer, the active layer comprises a source contact region, a drain contact region, and a semiconductor region disposed between the source contact region and the drain contact region, the source contact region and the drain contact region are both conductive, both of the source contact region and the drain contact region include a semiconductor substrate and ions distributed in the semiconductor substrate, the source electrode covers the source contact region directly, and the drain electrode covers the drain contact region directly.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 12, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Gao, Weifeng Zhou
  • Patent number: 9041202
    Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9040992
    Abstract: A display device includes a laminated wiring formed of a low-resistance conductive film, and a low-reflection film mainly containing Al and functioning as an antireflective film which are sequentially arranged on a transparent substrate, a wiring terminal part provided at an end part of the laminated wiring and has the same laminated structure as that of the laminated wiring, and an insulating film for covering the laminated wiring and the wiring terminal part, in which the insulating film side serves as a display surface side, the wiring terminal part has a first opening part penetrating the insulating film and the low-reflection film and reaching the low-resistance conductive film, and an outer peripheral portion of the first opening part has a laminated structure of the low-resistance conductive film, the low-reflection film, and the insulating film, in at least one part.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masami Hayashi, Kenichi Miyamoto, Kazushi Yamayoshi, Junichi Tsuchimichi
  • Patent number: 9012275
    Abstract: A method of forming TFT is provided. The TFT includes a gate electrode, a gate insulating layer, a first protective pattern, a second protective pattern, a source electrode, a drain electrode, a semiconductor channel layer, and a passivation layer. The first protective pattern and the second protective pattern are disposed on the gate insulating layer above the gate electrode. The source electrode is disposed on the gate insulating layer and the first protective pattern. The drain electrode is disposed on the gate insulating layer and the second protective pattern. The semiconductor channel layer is disposed on the gate insulating layer, the source electrode, and the drain electrode. In an extending direction from the source electrode to the drain electrode, a length of the first protective pattern is shorter than that of the source electrode, and a length of the second protective pattern is shorter than that of the drain electrode.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 21, 2015
    Assignee: AU Optronics Corp.
    Inventors: Chung-Tao Chen, Wu-Hsiung Lin, Po-Hsueh Chen
  • Patent number: 9006743
    Abstract: The present invention provides a thin film transistor including a first drain electrode, a second drain electrode, a first source electrode, and a second source electrode, wherein the first drain electrode and the first source electrode jointly define a first U-shaped channel facing toward a first direction. Wherein the second drain electrode and the second source electrode jointly define a second U-shaped channel facing a second direction which is different to the first direction, wherein the bottom width of the second U-shaped channel is larger then the bottom width of the first U-shaped channel. The present invention further provides an array substrate of the thin film transistor, and a method for making the array substrate. By way of the forgoing, short-circuit between the source electrode and the drain electrode resulted from the cleaning agent residue located in the bottom of the U-shaped channel of the thin film transistor can be avoided.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Jingfeng Xue
  • Patent number: 9006799
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 14, 2015
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 9000436
    Abstract: Disclosed is a thin film transistor including an active pattern including a first conductive region, a first channel region adjacent to the first conductive region, a second conductive region spaced apart from the first conductive region, a second channel region spaced apart from the first channel region, and a third conductive region spaced apart from the second conductive region, and a gate electrode positioned on the active pattern and including a first gate region crossing the first channel region, a second gate region crossing the second channel region, and a connection gate region connecting the first gate region. The connection gate region, the first gate region, and the second gate region together surround the second conductive region.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: So-Ra Kwon
  • Patent number: 9000523
    Abstract: An organic light-emitting display device including a TFT comprising an active layer, a gate electrode comprising a lower gate electrode and an upper gate electrode, and source and drain electrodes insulated from the gate electrode and contacting the active layer; an organic light-emitting device electrically connected to the TFT and comprising a pixel electrode formed in the same layer as where the lower gate electrode is formed; and a pad electrode electrically coupled to the TFT or the organic light emitting device and comprising a first pad electrode formed in the same layer as in which the lower gate electrode is formed, a second pad electrode formed in the same layer as in which the upper gate electrode is formed, and a third pad electrode comprising a transparent conductive oxide, the first, second, and third pad electrodes being sequentially stacked.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Jae-Hwan Oh
  • Patent number: 8980665
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata
  • Patent number: 8975142
    Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Abhijeet Paul, Abner Bello, Vimal K. Kamineni, Derya Deniz
  • Patent number: 8952387
    Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: February 10, 2015
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ce Ning, Xuehui Zhang, Jing Yang
  • Patent number: 8927353
    Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
  • Patent number: 8927983
    Abstract: Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole. Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.
    Type: Grant
    Filed: August 19, 2012
    Date of Patent: January 6, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wen-Chung Tang, Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Patent number: 8921859
    Abstract: An array substrate for an electrophoresis type display device includes a plurality of gate lines on a substrate; a gate insulating layer on the plurality of gate lines; a plurality of data lines on the gate insulating layer and crossing the plurality of gate lines to define a plurality of pixel regions; a thin film transistor corresponding to each pixel region, the thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes; a first passivation layer on the plurality of data lines; a second passivation layer on the first passivation layer, wherein the second passivation layer includes a first hole over the data line, and/or a second hole over the gate line with at least the gate insulating layer therebetween; and a pixel electrode on the second passivation layer and connected to the drain electrode, wherein a portion of the pixel electrode covers the first hole, and another portion of the pixel electrode covers the second hole.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: December 30, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Chul Kang, Sung-Jin Park
  • Patent number: 8912583
    Abstract: The present invention provides a thin-film transistor manufactured on a transparent substrate having a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate; wherein the channel region having channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film; the light blocking film is divided across the channel region; and interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d). Thereby, the cost for manufacturing the thin-film transistor is low, and the photo leak current of the thin-film transistor is suppressed.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: December 16, 2014
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Takahiro Korenari, Hiroshi Tanabe
  • Patent number: 8912538
    Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 16, 2014
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xiang Liu, Woobong Lee
  • Patent number: 8896778
    Abstract: It is an object to provide a liquid crystal display device including a thin film transistor with high electric characteristics and high reliability. As for a liquid crystal display device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, and a channel protective layer which is formed over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8895375
    Abstract: Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8896034
    Abstract: Radio frequency and microwave devices and methods of use are provided herein. According to some embodiments, the present technology may comprise an ohmic layer for use in a field effect transistor that includes a plurality of strips disposed on a substrate, the plurality of strips comprising alternating source strips and drain strips, with adjacent strips being spaced apart from one another to form a series of channels, a gate finger segment disposed in each of the series of channels, and a plurality of gate finger pads disposed in an alternating pattern around a periphery of the plurality of strips such that each gate finger segment is associated with two gate finger pads.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8890157
    Abstract: The present invention provides a pixel structure including a substrate, a thin-film transistor disposed on the substrate, a first insulating layer covering the thin-film transistor and the substrate, a common electrode, a connecting electrode, a second insulating layer, and a pixel electrode. The thin-film transistor includes a drain electrode. The first insulating layer has a first opening exposing the drain electrode. The common electrode and the connecting electrode are disposed on the first insulating layer. The connecting electrode extends into the first opening to be electrically connected to the drain electrode. The connecting electrode is electrically insulated from the common electrode. The second insulating layer covers the first insulating layer, the common electrode, the connecting electrode, and has a second opening exposing the connecting electrode. The pixel electrode is disposed on the second insulating layer and electrically connected to the connecting electrode through the second opening.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: HannStar Display Corp.
    Inventors: Hsuan-Chen Liu, Hsien-Cheng Chang, Da-Ching Tang, Chien-Hao Wu, Ching-Chao Wang, Jung-Chen Lin
  • Patent number: 8884286
    Abstract: A switching element includes an active pattern including a channel portion, a source portion connected to the channel portion, and a drain portion connected to the channel portion, the source portion, a gate electrode overlapping the channel portion of the active pattern, a gate insulation layer disposed between the channel portion of the active pattern and the gate electrode, a source electrode disposed on the source portion of the active pattern to make ohmic contact with the source portion, and a drain electrode disposed on the drain portion of the active pattern to make ohmic contact with the drain portion. The drain portion and the channel portion of the active pattern include the same or substantially the same material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yong-Su Lee, Su-Hyoung Kang, Yoon-Ho Khang, Hyun-Jae Na, Sang-Ho Park, Se-Hwan Yu, Myoung-Geun Cha
  • Patent number: 8884302
    Abstract: A semiconductor device including a first gate electrode and a second gate electrode formed apart from each other over an insulating surface, an oxide semiconductor film including a region overlapping with the first gate electrode with a gate insulating film interposed therebetween, a region overlapping with the second gate electrode with the gate insulating film interposed therebetween, and a region overlapping with neither the first gate electrode nor the second gate electrode, and an insulating film covering the gate insulating film, the first gate electrode, the second gate electrode, and the oxide semiconductor film, and being in direct contact with the oxide semiconductor film is provided.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: November 11, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Inoue, Hiroyuki Miyake, Kouhei Toyotaka
  • Patent number: 8865516
    Abstract: The present invention provides an oxide semiconductor capable of achieving a thin film transistor having stable transistor characteristics, a thin film transistor having a channel layer formed of the oxide semiconductor and a production method thereof, and a display device equipped with the thin film transistor. The oxide semiconductor of the present invention is an oxide semiconductor for a thin film transistor. The oxide semiconductor includes indium, gallium, zinc, and oxygen as constituent atoms, and the oxygen content of the oxide semiconductor is 87% to 95% of the stoichiometric condition set as 100%, in terms of atomic units.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: October 21, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshifumi Ohta, Go Mori, Hirohiko Nishiki, Yoshimasa Chikama, Tetsuya Aita, Masahiko Suzuki, Okifumi Nakagawa, Michiko Takei, Yoshiyuki Harumoto, Takeshi Hara
  • Patent number: 8866233
    Abstract: An object is to provide a semiconductor device having a novel structure which includes a combination of semiconductor elements with different characteristics and is capable of realizing higher integration. A semiconductor device includes a first transistor, which includes a first channel formation region including a first semiconductor material, and a first gate electrode, and a second transistor, which includes one of a second source electrode and a second drain electrode combined with the first gate electrode, and a second channel formation region including a second semiconductor material and electrically connected to the second source electrode and the second drain electrode.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8853687
    Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio ( R , R ? [ mol ? ? % ] = [ In ] [ In + Zn + Sn ] × 100 ) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, ( R , R ? [ mol ? ? % ] = [ In ] [ In + Zn + Sn ] / 100 ) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Doo Hyoung Lee, Chan Woo Yang, Seung-Ho Jung, Doo Na Kim, Bo Sung Kim, Eun Hye Park
  • Patent number: 8853703
    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji-Young Park, Yu-Gwang Jeong, Sang Gab Kim, Joon Geol Lee
  • Patent number: 8847316
    Abstract: An object of the present invention is to provide a semiconductor device having high operation characteristic and reliability. The measures taken are: A pixel capacitor is formed between an electrode comprising anodic capable material over an organic resin film, an anodic oxide film of the electrode and a pixel electrode above. Since the anodic oxide film is anodically oxidized by applied voltage per unit time at 15V/min, there is no wrap around on the electrode, and film peeling can be prevented.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Shunpei Yamazaki, Jun Koyama, Mitsuaki Osame, Yukio Tanaka, Yoshiharu Hirakata
  • Patent number: 8841678
    Abstract: A thin-film transistor device includes: a gate electrode above a substrate; a gate insulating film on the gate electrode; a crystalline silicon thin film including a channel region which is provided on the gate insulating film; semiconductor films on at least the channel region; an insulating film made of an organic material which is provided over the channel region and above the semiconductor films; a source electrode over at least an end portion of the insulating film; and a drain electrode over at least the other end portion of the insulating film and facing the source electrode. The semiconductor films include at least a first semiconductor film and a second semiconductor film provided on the first semiconductor film. A relationship ECP<EC1 is satisfied where ECP and EC1 denote energy levels at lower ends of conduction bands of the crystalline silicon thin film and the first semiconductor film, respectively.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 23, 2014
    Assignees: Panasonic Corporation, Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Arinobu Kanegae, Takahiro Kawashima, Hiroshi Hayashi, Genshirou Kawachi
  • Patent number: 8841679
    Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel includes: an insulation substrate including a display area with a plurality of pixels and a peripheral area around the display area; a gate line and a data line positioned in the display area of the insulation substrate; a first driving signal transfer line and a second driving signal transfer line positioned in the peripheral area of the insulation substrate; a first insulating layer positioned on the gate line and the data line; and a first photosensitive film positioned on the first driving signal transfer line and the second driving signal transfer line, in which the first photosensitive film is disposed only in the peripheral area.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Yong Shin, Woo-Sung Sohn, Hong Min Yoon, Hui Gyeong Yun
  • Patent number: 8835236
    Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8829520
    Abstract: A thin film transistor (TFT) includes a gate, a semiconductor layer, an insulating layer, a source, a drain, and a current reduction layer. The insulating layer is disposed between the gate and the semiconductor layer. The source is connected to the semiconductor layer. The drain is connected to the semiconductor layer, and the source and the drain are separated from each other. The current reduction layer has a first part and a second part. The first part is disposed between the semiconductor layer and at least a part of the source, and the second part is disposed between the semiconductor layer and at least a part of the drain.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: September 9, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Ted-Hong Shinn
  • Patent number: 8803143
    Abstract: A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8803149
    Abstract: A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichiro Sakata
  • Patent number: 8803148
    Abstract: A thin film transistor may include a substrate, a buffer layer on the substrate, a semiconductor layer formed on the buffer layer, a gate insulating pattern on the semiconductor layer, a gate electrode on the gate insulating pattern, an interlayer insulating layer covering the gate electrode and the gate insulating pattern, the interlayer insulating layer having a contact hole and an opening extending therethrough, the contact hole exposing a source area and a drain area of the semiconductor layer, and the opening exposing a channel area of the semiconductor layer, and a source electrode and a drain electrode formed on the interlayer insulating layer, the source electrode being connected with the source area and the drain electrode being connected with the drain area of the semiconductor layer.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: August 12, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee, Heung-Yeol Na
  • Patent number: 8792060
    Abstract: A liquid crystal display device with a built-in touch screen, which uses a common electrode as a touch-sensing electrode including an intersection of a gate line and a data line to define a pixel region, a bridge line disposed in a central portion of the pixel, an insulating layer formed on the bridge line, a first contact hole disposed through the insulating layer to expose a predetermined portion of an upper surface of the bridge line, a contact metal on the insulating layer and inside the first contact hole, the contact metal electrically connected with the bridge line, a first passivation layer on the contact metal, a second contact hole disposed through the first passivation layer to expose a predetermined portion of an upper surface of the contact metal, a common electrode on the first passivation layer and inside the second contact hole, a conductive line electrically connected with the common electrode, and a second passivation layer on the first passivation layer and the conductive line, wherein the
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 29, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Kum Mi Oh, Jae Hoon Park, Han Seok Lee, Hee Sun Shin, Won Keun Park
  • Patent number: 8785264
    Abstract: According to an embodiment of the disclosed technology, a manufacture method of an organic thin film transistor array substrate is provided. The method comprises: forming a first pixel electrode, a source electrode, a drain electrode and a data line in a first patterning process; forming an organic semiconductor island and a gate insulating island in a second patterning process; forming a data pad region in a third patterning process; and forming a second pixel electrode, a gate electrode and a gate line in a fourth patterning process.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 22, 2014
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xuehui Zhang
  • Patent number: 8785939
    Abstract: A pixel electrode is provided, with a nanostructure-film deposited over an active matrix substrate, such that the pixel electrode makes electrical contact with an underlying layer. Similarly, auxiliary data pads and auxiliary gate pads are provided, which also have nanostructure-films deposited over an active matrix substrate, such that they make electrical contact with underlying layers.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Bae Park, George Gruner, Liangbing Hu
  • Patent number: 8772752
    Abstract: An object is to prevent light leakage caused due to misregistration even when the width of a black matrix layer is not expanded to a designed value or larger. One embodiment of the present invention is a semiconductor device including a single-gate thin film transistor in which a first semiconductor layer is sandwiched between a bottom-gate electrode and a first black matrix layer. The first semiconductor layer and the first black matrix layer overlap with each other.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: July 8, 2014
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hidekazu Miyairi, Atsushi Hirose, Yoshitaka Yamamoto, Tomohiro Kimura
  • Patent number: 8772784
    Abstract: One of factors that increase the contact resistance at the interface between a first semiconductor layer where a channel is formed and source and drain electrode layers is a film with high electric resistance formed by dust or impurity contamination of a surface of a metal material serving as the source and drain electrode layers. As a solution, a first protective layer and a second protective layer including a second semiconductor having a conductivity that is less than or equal to that of the first semiconductor layer is stacked successively over source and drain electrode layers without exposed to air, the stack of films is used for the source and drain electrode layers.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8772897
    Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Won Kim, Kap-Soo Yoon, Woo-Geun Lee, Yeong-Keun Kwon, Hye-Young Ryu, Jin-Won Lee, Hyun-Jung Lee
  • Patent number: 8749725
    Abstract: A flat panel display apparatus including a gate electrode on a substrate, a first insulating layer and a semiconductor layer sequentially stacked on the gate electrode and including a transparent conductive oxide, a capacitor first electrode extending on a plane on which the gate electrode extends, and a capacitor second electrode extending on a plane on which the semiconductor layer extends and including a material of the semiconductor layer, wherein the first insulating layer is between the capacitor second electrode and the semiconductor layer, source and drain electrodes that are separated by a second insulating layer and are connected to the semiconductor layer and the capacitor second electrode, a third insulating layer covering the source and drain electrodes, and a pixel electrode electrically connected to the source or drain electrode on the third insulating layer and being electrically connected to one of the source electrode and/or the drain electrode.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Sun Yoon, Seong-Min Wang
  • Patent number: 8741672
    Abstract: Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 3, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joo-Han Kim, Hwa-Dong Jung, Wan-Soon Lim, Jee-Hun Lim, Joo Seok Yeom, Tae-Kyung Yim, Jae-Hak Lee, Hyuk Soon Kwon, Hyoung Cheol Lee, Jeong-Ju Park, Se-Myung Kwon, So-Young Koo
  • Patent number: 8742424
    Abstract: The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 3, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Chikao Yamasaki, Tetsuo Kikuchi, Shinya Tanaka, Junya Shimada
  • Patent number: 8742423
    Abstract: In a thin-film transistor array according to an embodiment of the present invention, thin-film transistors are disposed in a matrix array, the thin-film transistor including a gate electrode that is formed on a substrate, a gate insulating layer that is formed on the gate electrode, a source electrode that is formed on the gate insulating layer, a pixel electrode that is formed on the gate insulating layer, a drain electrode that is connected to the pixel electrode, and a semiconductor layer that is formed between the source electrode and the drain electrode, the gate electrode is connected to a gate line while the source electrode is connected to a source line, the thin-film transistor is formed within a region of the source line and the thin-film transistor array includes a stripe insulating film such that the source line and the semiconductor layer are covered with the stripe insulating film.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: June 3, 2014
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Ryohei Matsubara, Mamoru Ishizaki
  • Patent number: 8735889
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 8728861
    Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 20, 2014
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Burhan Bayraktaroglu, Kevin Leedy